Hard mask etch and dielectric etch aware overlap for via and metal layers

    公开(公告)号:US09817927B2

    公开(公告)日:2017-11-14

    申请号:US14841037

    申请日:2015-08-31

    CPC classification number: G06F17/5009 G03F1/36 G06F17/5081

    Abstract: A method and apparatus for generating a final dielectric etch compensation table and a final hard mask etch compensation table for either OPC or MPC process flows are provided. Embodiments include performing an overlap pattern classification on a wafer; calibrating a dielectric etch bias or a hard mask etch bias based on the pattern classification; comparing either a CD overlap of a via layer with a metal layer and a CD overlap of the via layer with a lower connecting metal layer or a CD overlap of the metal layer with an upper connecting via layer and a CD overlap of the metal layer with the via layer against a criteria; outputting final dielectric etch compensation and hard mask etch compensation tables to either OPC or MPC process flows; and repeating the steps of calibrating, comparing, and outputting for either the via layer or metal layer remaining.

    OPTICAL PROXIMITY CORRECTION FOR CONNECTING VIA BETWEEN LAYERS OF A DEVICE
    2.
    发明申请
    OPTICAL PROXIMITY CORRECTION FOR CONNECTING VIA BETWEEN LAYERS OF A DEVICE 审中-公开
    用于通过设备层连接的光学近似校正

    公开(公告)号:US20150006138A1

    公开(公告)日:2015-01-01

    申请号:US13932141

    申请日:2013-07-01

    CPC classification number: G03F7/70441 G03F1/36

    Abstract: Approaches for simulating a photolithographic process are provided. Specifically, provided is an optical proximity correction (OPC) model that includes kernel parameters corresponding to inter-layer activity and an etch process for a connecting via of an integrated circuit (IC). A resultant intensity is determined for a corresponding plurality of process variations corresponding to the interlayer activity and the etch process. As such, the OPC model considers both interlay activity and etch process.

    Abstract translation: 提供了用于模拟光刻工艺的方法。 具体地,提供了包括对应于层间活动的核参数和用于集成电路(IC)的连接通路的蚀刻处理的光学邻近校正(OPC)模型。 对于与层间活性和蚀刻工艺相对应的相应多个工艺变化确定合成强度。 因此,OPC模型考虑了interlay活动和蚀刻过程。

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