公开(公告)号：US20160365288A1

公开(公告)日：2016-12-15

申请号：US14737551

申请日：2015-06-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui WANG ,  Ryan Ryoung-han KIM ,  Linus JANG ,  Jason CANTONE ,  Lei SUN ,  Seowoo NAM

IPC: H01L21/8238 ,  H01L23/528 ,  H01L21/02 ,  H01L27/092 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/092 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/3212 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

Abstract translation: 公开了使用虚拟栅极作为互连的工艺及其制造方法。 实施例包括在半导体衬底上形成在单元边界处的虚拟栅极结构，每个虚拟栅极结构包括一组侧壁间隔件和设置在侧壁间隔件之间的盖; 在第一伪栅极结构的第一侧上去除第一侧壁间隔物或第一盖的至少一部分，并在第一伪栅极结构上形成第一栅极接触沟槽; 以及用金属填充所述第一栅极接触沟槽以形成第一栅极接触。

公开(公告)号：US20170141110A1

公开(公告)日：2017-05-18

申请号：US15418996

申请日：2017-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui WANG ,  Ryan Ryoung-han KIM ,  Linus JANG ,  Jason CANTONE ,  Lei SUN ,  Seowoo NAM

IPC: H01L27/092 ,  H01L27/02 ,  H01L29/06 ,  H01L21/321 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L23/528 ,  H01L29/49

CPC classification number: H01L27/092 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/3212 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

公开(公告)号：US20150097249A1

公开(公告)日：2015-04-09

申请号：US14046351

申请日：2013-10-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan KIM ,  Jason CANTONE

IPC: H01L21/8234 ,  H01L27/088 ,  H01L27/02

CPC classification number: H01L21/823475 ,  H01L27/0207 ,  H01L27/088

Abstract: Methodologies for forming a cross coupling gate and a resulting device are disclosed. Embodiments include: providing a plurality of gates extending vertically on a plurality of equally spaced horizontal positions of an IC; providing a cross-couple region of a gate of the plurality of gates, the cross-couple region including a portion of the gate extending from a first horizontal position of the horizontal positions to a second horizontal position of the horizontal positions; and providing at least one of the plurality of gates with an overlap of first and second segments of the at least one gate, the first and second segments being designated to be decomposed using different colors.

Abstract translation: 公开了用于形成交叉耦合栅极和所得到的器件的方法。 实施例包括：提供在IC的多个等间隔的水平位置上垂直延伸的多个门; 提供多个栅极的栅极的交叉耦合区域，所述交叉耦合区域包括从所述水平位置的第一水平位置延伸到所述水平位置的第二水平位置的所述栅极的一部分; 以及提供所述多个门中的至少一个具有所述至少一个栅极的第一和第二段的重叠，所述第一和第二段被指定为使用不同的颜色分解。