公开(公告)号：US20140141605A1

公开(公告)日：2014-05-22

申请号：US13682769

申请日：2012-11-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chang Seo PARK ,  Linus JANG ,  Jin CHO

IPC: H01L29/66

CPC classification number: H01L29/66742 ,  H01L29/66795

Abstract: Approaches for forming a FinFET device using double patterning memorization techniques are provided. Specifically, a device will initially be formed by defining a set of fins, depositing a poly-silicon layer, and depositing a hardmask. Thereafter, a front end of the line (FEOL) lithography-etch, lithography-etch (LELE) process will be performed to form a set of trenches in the device. The set of trenches will be filled with an oxide layer that is subsequently polished. Thereafter, the device is selectively etched to yield a (e.g., poly-silicon) gate pattern.

Abstract translation: 提供了使用双重图案记忆技术形成FinFET器件的方法。 具体来说，首先将通过限定一组翅片，沉积多晶硅层和沉积硬掩模来形成器件。 此后，将执行线的前端（FEOL）光刻蚀刻，光刻蚀刻（LELE）处理以在器件中形成一组沟槽。 该组沟槽将填充随后抛光的氧化物层。 此后，选择性地蚀刻器件以产生（例如，多晶硅）栅极图案。

公开(公告)号：US20160336172A1

公开(公告)日：2016-11-17

申请号：US14712197

申请日：2015-05-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Linus JANG ,  Sanggil BAE ,  Daeyoup LEE

IPC: H01L21/027 ,  G03F7/09 ,  G03F7/11 ,  H01L21/033 ,  H01L29/06

CPC classification number: H01L21/0273 ,  G03F7/0752 ,  G03F7/091 ,  G03F7/094 ,  G03F7/11 ,  G03F7/40 ,  G03F7/42 ,  H01L21/0332 ,  H01L21/0337 ,  H01L22/12 ,  H01L22/20 ,  H01L29/0649 ,  H01L29/0692

Abstract: Lithography stack, intermediate semiconductor devices, and methods of fabrication are provided. The method includes obtaining an intermediate semiconductor device with a substrate, applying a spin on carbon layer over the substrate, and applying a hardmask layer over the spin on carbon layer. The intermediate semiconductor device includes a substrate, a spin on carbon layer over the substrate, and a hardmask layer over the spin on carbon layer. The lithography stack includes a spin on carbon layer, an invisible hardmask layer over the spin on carbon layer, and a photoresist layer over the invisible hardmask layer.

Abstract translation: 提供了平版印刷叠层，中间半导体器件和制造方法。 该方法包括获得具有衬底的中间半导体器件，在衬底上施加在碳层上的自旋，以及在碳层上的自旋上施加硬掩模层。 中间半导体器件包括衬底，在衬底上的自旋碳层，以及在碳层上的旋涂上的硬掩模层。 光刻堆叠包括在碳层上的自旋，在碳层上的自旋上的不可见的硬掩模层，以及在不可见的硬掩模层上的光致抗蚀剂层。

公开(公告)号：US20170141110A1

公开(公告)日：2017-05-18

申请号：US15418996

申请日：2017-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui WANG ,  Ryan Ryoung-han KIM ,  Linus JANG ,  Jason CANTONE ,  Lei SUN ,  Seowoo NAM

IPC: H01L27/092 ,  H01L27/02 ,  H01L29/06 ,  H01L21/321 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L23/528 ,  H01L29/49

CPC classification number: H01L27/092 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/3212 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

公开(公告)号：US20180226294A1

公开(公告)日：2018-08-09

申请号：US15425478

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene STEPHENS ,  David Michael PERMANA ,  Guillaume BOUCHE ,  Andy WEI ,  Mark ZALESKI ,  Anbu Selvam KM MAHALINGAM ,  Craig Michael CHILD, JR. ,  Roderick Alan AUGUR ,  Shyam PAL ,  Linus JANG ,  Xiang HU ,  Akshey SEHGAL

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.

公开(公告)号：US20160365288A1

公开(公告)日：2016-12-15

申请号：US14737551

申请日：2015-06-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui WANG ,  Ryan Ryoung-han KIM ,  Linus JANG ,  Jason CANTONE ,  Lei SUN ,  Seowoo NAM

IPC: H01L21/8238 ,  H01L23/528 ,  H01L21/02 ,  H01L27/092 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/092 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/3212 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

Abstract translation: 公开了使用虚拟栅极作为互连的工艺及其制造方法。 实施例包括在半导体衬底上形成在单元边界处的虚拟栅极结构，每个虚拟栅极结构包括一组侧壁间隔件和设置在侧壁间隔件之间的盖; 在第一伪栅极结构的第一侧上去除第一侧壁间隔物或第一盖的至少一部分，并在第一伪栅极结构上形成第一栅极接触沟槽; 以及用金属填充所述第一栅极接触沟槽以形成第一栅极接触。