DOUBLE GATE VERTICAL FINFET SEMICONDUCTOR STRUCTURE

    公开(公告)号:US20180331212A1

    公开(公告)日:2018-11-15

    申请号:US15592444

    申请日:2017-05-11

    CPC classification number: H01L29/7827 H01L29/4966 H01L29/66666

    Abstract: A semiconductor structure includes a substrate and a vertical FinFET disposed over the substrate. The vertical FinFET includes: a bottom source/drain (S/D) region disposed over the substrate, a fin extending vertically upwards from the bottom S/D region, the fin having a first (1st) sidewall, a second (2nd) sidewall and a top portion, an upper S/D region disposed over the top portion of the fin, the fin defining a channel between the bottom S/D region and the upper S/D region, a 1st gate structure having a 1st metal gate, the 1st gate structure disposed on the 1st sidewall of the fin, and a 2nd gate structure having a 2nd metal gate, the 2nd gate structure disposed on the 2nd sidewall of the fin. The 1st and 2nd metal gates are electrically isolated from each other by the fin.

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