-
公开(公告)号:US20180308759A1
公开(公告)日:2018-10-25
申请号:US15496429
申请日:2017-04-25
Applicant: GLOBALFOUNDRIES Inc.
Inventor: Hui ZANG , Josef WATTS
IPC: H01L21/8234 , H01L29/66 , H01L21/311 , H01L21/28
CPC classification number: H01L21/823437 , H01L21/28247 , H01L21/31111 , H01L21/823431 , H01L21/823481 , H01L27/0886 , H01L27/0924 , H01L27/10879 , H01L29/6653 , H01L29/66545 , H01L29/7831 , H01L29/785
Abstract: A method includes providing a semiconductor structure having a substrate and a plurality of fins extending upwards from the substrate. A CT pillar layer is disposed over the semiconductor structure. A CT mask is lithographically patterned over the CT pillar layer. The CT mask is anisotropically etched to remove exposed portions of the CT pillar layer and to form a CT pillar between the fins. A dummy gate structure is disposed across the CT pillar. The dummy gate structure is replaced with first and second metal gate structures that are electrically isolated from each other by the CT pillar.
-
公开(公告)号:US20180331212A1
公开(公告)日:2018-11-15
申请号:US15592444
申请日:2017-05-11
Applicant: GLOBALFOUNDRIES Inc.
Inventor: Hui ZANG , Josef WATTS
CPC classification number: H01L29/7827 , H01L29/4966 , H01L29/66666
Abstract: A semiconductor structure includes a substrate and a vertical FinFET disposed over the substrate. The vertical FinFET includes: a bottom source/drain (S/D) region disposed over the substrate, a fin extending vertically upwards from the bottom S/D region, the fin having a first (1st) sidewall, a second (2nd) sidewall and a top portion, an upper S/D region disposed over the top portion of the fin, the fin defining a channel between the bottom S/D region and the upper S/D region, a 1st gate structure having a 1st metal gate, the 1st gate structure disposed on the 1st sidewall of the fin, and a 2nd gate structure having a 2nd metal gate, the 2nd gate structure disposed on the 2nd sidewall of the fin. The 1st and 2nd metal gates are electrically isolated from each other by the fin.
-