公开(公告)号：US10651046B2

公开(公告)日：2020-05-12

申请号：US16154237

申请日：2018-10-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hsueh-Chung Chen ,  Brendan O'Brien ,  Martin O'Toole ,  Keith Donegan

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/033

Abstract: Methods of self-aligned multiple patterning. A mandrel is formed over a hardmask, and a planarizing layer is formed over the mandrel and the hardmask. The planarizing layer is patterned to form first and second trenches exposing respective first and second lengthwise sections of the mandrel. A portion of the patterned planarizing layer covers a third lengthwise section of the mandrel arranged between the first and second lengthwise sections of the mandrel. After patterning the planarizing layer, the first and second lengthwise sections of the mandrel are removed with an etching process to define a pattern including a mandrel line exposing respective first portions of the hardmask. The third lengthwise section of the mandrel is masked by the portion of the planarizing layer during the etching process, and the third lengthwise section covers a second portion of the hardmask arranged along the mandrel line between the first portions of the hardmask.

公开(公告)号：US09287109B2

公开(公告)日：2016-03-15

申请号：US13798764

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Torsten Huisinga ,  Keith Donegan ,  Robert Seidel

IPC: H01L21/308 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/02079 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144

Abstract: One method disclosed herein includes forming a layer of insulating material above a semiconductor substrate, forming a hard mask layer comprised of a metal-containing material above the layer of insulating material, forming a blanket protection layer on the hard mask layer, forming a masking layer above the protection layer, performing at least one etching process on the masking layer to form a patterned masking layer having an opening that stops on and exposes a portion of the blanket protection layer, confirming that the patterned masking layer is properly positioned relative to at least one underlying structure or layer and, after confirming that the patterned masking layer is properly positioned, performing at least one etching process through the patterned masking layer to pattern at least the blanket protection layer.

Abstract translation: 本文公开的一种方法包括在半导体衬底上形成绝缘材料层，在绝缘材料层之上形成由含金属材料构成的硬掩模层，在硬掩模层上形成覆盖层保护层，形成掩模层 在保护层上方，在掩模层上执行至少一个蚀刻工艺，以形成图案化掩模层，该掩模层具有停止并暴露橡皮布保护层的一部分的开口，证实图案化掩模层相对于至少 一个底层结构或层，并且在确认图案化掩模层被正确定位之后，通过图案化掩模层执行至少一个蚀刻工艺，以至少对覆盖保护层进行图案化。

公开(公告)号：US20140264758A1

公开(公告)日：2014-09-18

申请号：US13798764

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Torsten Huisinga ,  Keith Donegan ,  Robert Seidel

IPC: H01L21/308

CPC classification number: H01L21/02079 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144

Abstract: One method disclosed herein includes forming a layer of insulating material above a semiconductor substrate, forming a hard mask layer comprised of a metal-containing material above the layer of insulating material, forming a blanket protection layer on the hard mask layer, forming a masking layer above the protection layer, performing at least one etching process on the masking layer to form a patterned masking layer having an opening that stops on and exposes a portion of the blanket protection layer, confirming that the patterned masking layer is properly positioned relative to at least one underlying structure or layer and, after confirming that the patterned masking layer is properly positioned, performing at least one etching process through the patterned masking layer to pattern at least the blanket protection layer.

Abstract translation: 本文公开的一种方法包括在半导体衬底上形成绝缘材料层，在绝缘材料层之上形成由含金属材料构成的硬掩模层，在硬掩模层上形成覆盖层保护层，形成掩模层 在保护层上方，在掩模层上执行至少一个蚀刻工艺，以形成图案化掩模层，该掩模层具有停止并暴露橡皮布保护层的一部分的开口，证实图案化掩模层相对于至少 一个底层结构或层，并且在确认图案化掩模层被正确定位之后，通过图案化掩模层执行至少一个蚀刻工艺，以至少对覆盖保护层进行图案化。

公开(公告)号：US10199270B2

公开(公告)日：2019-02-05

申请号：US15605327

申请日：2017-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Colin Bombardier ,  Ming He ,  Vikrant Chauhan ,  Anbu Selvam KM Mahalingam ,  Keith Donegan

IPC: H01L21/768 ,  H01L21/66 ,  H01L23/522 ,  H01L23/528

Abstract: Interconnect structures and methods of fabricating an interconnect structure. First and second non-mandrel interconnects are formed in an interlayer dielectric layer. The first non-mandrel interconnect and the second non-mandrel interconnect have respective side surfaces that extend in a first direction. The connector interconnect extends in a second direction transverse to the first direction from the side surface of the first non-mandrel interconnect to the side surface of the second non-mandrel interconnect.

公开(公告)号：US20180342421A1

公开(公告)日：2018-11-29

申请号：US15605327

申请日：2017-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Colin Bombardier ,  Ming He ,  Vikrant Chauhan ,  Anbu Selvam KM Mahalingam ,  Keith Donegan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/66

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L22/32 ,  H01L23/5226 ,  H01L23/528

Abstract: Interconnect structures and methods of fabricating an interconnect structure. First and second non-mandrel interconnects are formed in an interlayer dielectric layer. The first non-mandrel interconnect and the second non-mandrel interconnect have respective side surfaces that extend in a first direction. The connector interconnect extends in a second direction transverse to the first direction from the side surface of the first non-mandrel interconnect to the side surface of the second non-mandrel interconnect.