公开(公告)号：US20170005159A1

公开(公告)日：2017-01-05

申请号：US15266439

申请日：2016-09-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert Seidel ,  Torsten Huisinga

IPC: H01L49/02 ,  H01L21/768

CPC classification number: H01L28/40 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/7685 ,  H01L28/75

Abstract: A semiconductor device includes a first metallization layer including a first dielectric layer. A first conductive layer and a first conductive structure are embedded in the first dielectric layer. A second dielectric layer is disposed on the first metallization layer. A second conductive layer is disposed on the second dielectric layer and has a lateral dimension in a lateral direction larger than a lateral dimension of the first conductive layer in the lateral direction. A third dielectric layer is disposed on the second conductive layer. A first contact is disposed in the third dielectric layer and extends through the second conductive structure in a first peripheric region thereof that does not overlap the first conductive layer to contact the first conductive structure. A capacitor structure includes the first conductive layer, the second dielectric layer and the second conductive layer.

Abstract translation: 半导体器件包括包括第一介电层的第一金属化层。 第一导电层和第一导电结构嵌入在第一介电层中。 第二介电层设置在第一金属化层上。 第二导电层设置在第二电介质层上，并且在横向上具有比横向上的第一导电层的横向尺寸更大的横向尺寸。 第三介电层设置在第二导电层上。 第一触点设置在第三电介质层中，并且在其第一外围区域中延伸穿过第二导电结构，该第一外围区域不与第一导电层重叠以接触第一导电结构。 电容器结构包括第一导电层，第二介电层和第二导电层。

公开(公告)号：US09685497B2

公开(公告)日：2017-06-20

申请号：US15266439

申请日：2016-09-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert Seidel ,  Torsten Huisinga

IPC: H01L49/02 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L28/40 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/7685 ,  H01L28/75

Abstract: A semiconductor device includes a first metallization layer including a first dielectric layer. A first conductive layer and a first conductive structure are embedded in the first dielectric layer. A second dielectric layer is disposed on the first metallization layer. A second conductive layer is disposed on the second dielectric layer and has a lateral dimension in a lateral direction larger than a lateral dimension of the first conductive layer in the lateral direction. A third dielectric layer is disposed on the second conductive layer. A first contact is disposed in the third dielectric layer and extends through the second conductive structure in a first peripheric region thereof that does not overlap the first conductive layer to contact the first conductive structure. A capacitor structure includes the first conductive layer, the second dielectric layer and the second conductive layer.

公开(公告)号：US20160099302A1

公开(公告)日：2016-04-07

申请号：US14507927

申请日：2014-10-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert Seidel ,  Torsten Huisinga

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/40 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/7685 ,  H01L28/75

Abstract: A method of manufacturing a semiconductor device comprising a capacitor structure is provided, including the steps of forming a first metallization layer comprising a first dielectric layer and a first conductive layer functioning as a lower electrode for the capacitor structure over a semiconductor substrate, forming a barrier layer functioning as a capacitor insulator for the capacitor structure on the first metallization layer, forming a metal layer on the barrier layer and etching the metal layer to form an upper electrode of the capacitor structure.

Abstract translation: 提供一种制造包括电容器结构的半导体器件的方法，包括以下步骤：在半导体衬底上形成第一金属化层，其包括第一电介质层和用作电容器结构的下电极的第一导电层，形成屏障 层作为第一金属化层上的电容器结构的电容绝缘体，在阻挡层上形成金属层，并蚀刻金属层以形成电容器结构的上部电极。

公开(公告)号：US09287109B2

公开(公告)日：2016-03-15

申请号：US13798764

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Torsten Huisinga ,  Keith Donegan ,  Robert Seidel

IPC: H01L21/308 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/02079 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144

Abstract: One method disclosed herein includes forming a layer of insulating material above a semiconductor substrate, forming a hard mask layer comprised of a metal-containing material above the layer of insulating material, forming a blanket protection layer on the hard mask layer, forming a masking layer above the protection layer, performing at least one etching process on the masking layer to form a patterned masking layer having an opening that stops on and exposes a portion of the blanket protection layer, confirming that the patterned masking layer is properly positioned relative to at least one underlying structure or layer and, after confirming that the patterned masking layer is properly positioned, performing at least one etching process through the patterned masking layer to pattern at least the blanket protection layer.

Abstract translation: 本文公开的一种方法包括在半导体衬底上形成绝缘材料层，在绝缘材料层之上形成由含金属材料构成的硬掩模层，在硬掩模层上形成覆盖层保护层，形成掩模层 在保护层上方，在掩模层上执行至少一个蚀刻工艺，以形成图案化掩模层，该掩模层具有停止并暴露橡皮布保护层的一部分的开口，证实图案化掩模层相对于至少 一个底层结构或层，并且在确认图案化掩模层被正确定位之后，通过图案化掩模层执行至少一个蚀刻工艺，以至少对覆盖保护层进行图案化。

公开(公告)号：US20140264758A1

公开(公告)日：2014-09-18

申请号：US13798764

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Torsten Huisinga ,  Keith Donegan ,  Robert Seidel

IPC: H01L21/308

CPC classification number: H01L21/02079 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144

Abstract: One method disclosed herein includes forming a layer of insulating material above a semiconductor substrate, forming a hard mask layer comprised of a metal-containing material above the layer of insulating material, forming a blanket protection layer on the hard mask layer, forming a masking layer above the protection layer, performing at least one etching process on the masking layer to form a patterned masking layer having an opening that stops on and exposes a portion of the blanket protection layer, confirming that the patterned masking layer is properly positioned relative to at least one underlying structure or layer and, after confirming that the patterned masking layer is properly positioned, performing at least one etching process through the patterned masking layer to pattern at least the blanket protection layer.

Abstract translation: 本文公开的一种方法包括在半导体衬底上形成绝缘材料层，在绝缘材料层之上形成由含金属材料构成的硬掩模层，在硬掩模层上形成覆盖层保护层，形成掩模层 在保护层上方，在掩模层上执行至少一个蚀刻工艺，以形成图案化掩模层，该掩模层具有停止并暴露橡皮布保护层的一部分的开口，证实图案化掩模层相对于至少 一个底层结构或层，并且在确认图案化掩模层被正确定位之后，通过图案化掩模层执行至少一个蚀刻工艺，以至少对覆盖保护层进行图案化。

公开(公告)号：US09478602B2

公开(公告)日：2016-10-25

申请号：US14507927

申请日：2014-10-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert Seidel ,  Torsten Huisinga

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/7685 ,  H01L28/75

Abstract: A method of manufacturing a semiconductor device comprising a capacitor structure is provided, including the steps of forming a first metallization layer comprising a first dielectric layer and a first conductive layer functioning as a lower electrode for the capacitor structure over a semiconductor substrate, forming a barrier layer functioning as a capacitor insulator for the capacitor structure on the first metallization layer, forming a metal layer on the barrier layer and etching the metal layer to form an upper electrode of the capacitor structure.

Abstract translation: 提供一种制造包括电容器结构的半导体器件的方法，包括以下步骤：在半导体衬底上形成第一金属化层，其包括第一电介质层和用作电容器结构的下电极的第一导电层，形成屏障 层作为第一金属化层上的电容器结构的电容绝缘体，在阻挡层上形成金属层，并蚀刻金属层以形成电容器结构的上部电极。