公开(公告)号：US20160268260A1

公开(公告)日：2016-09-15

申请号：US15051420

申请日：2016-02-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwanyong LIM ,  Murat Kerem AKARVARDAR

IPC: H01L27/092 ,  H01L29/167 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823892 ,  H01L29/167

Abstract: Reducing a chance of punch-through in a FinFET structure includes providing a substrate, creating a blanket layer of semiconductor material with impurities therein over the substrate, masking a portion of the blanket layer, creating epitaxial semiconductor material on an unmasked portion of the structure, removing the mask, and etching the structure to create n-type raised structure(s) and p-type raised structure(s), a bottom portion of the raised structure(s) being surrounded by isolation material. A middle portion of the raised structure(s) includes a semiconductor material with impurities therein, the middle portion extending across the raised structure(s), and a top portion including a semiconductor material lacking added impurities.

Abstract translation: 减少在FinFET结构中穿透的机会包括提供衬底，在衬底上产生其中杂质的半导体材料的覆盖层，掩蔽覆盖层的一部分，在结构的未屏蔽部分上产生外延半导体材料， 去除掩模，并蚀刻该结构以产生n型凸起结构和p型凸起结构，凸起结构的底部被隔离材料包围。 凸起结构的中间部分包括其中具有杂质的半导体材料，中间部分延伸穿过凸起结构，以及包括不含添加杂质的半导体材料的顶部。

公开(公告)号：US20160049401A1

公开(公告)日：2016-02-18

申请号：US14459005

申请日：2014-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu SUNG ,  Hiroaki NIIMI ,  Kwanyong LIM

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L21/02 ,  H01L29/06 ,  H01L27/11 ,  H01L21/285

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/28512 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823835 ,  H01L21/823871 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636

Abstract: A non-planar semiconductor structure, for example, a dual FinFET structure, includes a n-type semiconductor device and a p-type semiconductor device. Metal-insulator-semiconductor (MIS) contacts provide electrical connection to the n-type device, and metal-semiconductor (MS) contacts provide electrical connection to the p-type device. The metal of both MIS and MS contacts is a same n-type work function metal. In one example, the semiconductor of the MIS contact includes epitaxial silicon germanium with a relatively low percentage of germanium, the insulator of the MIS contact includes titanium dioxide, the semiconductor for the MS contact includes silicon germanium with a relatively high percentage of germanium or pure germanium, and the metal for both contacts includes a n-type work function metal.

Abstract translation: 非平面半导体结构，例如双重FinFET结构，包括n型半导体器件和p型半导体器件。 金属绝缘体半导体（MIS）触点提供与n型器件的电连接，并且金属半导体（MS）触点提供与p型器件的电连接。 MIS和MS触点的金属都是相同的n型工作功能金属。 在一个示例中，MIS接触的半导体包括具有相对较低百分比的锗的外延硅锗，MIS接触的绝缘体包括二氧化钛，用于MS接触的半导体包括具有相对较高百分比的锗或纯度的硅锗 锗，并且用于两个触点的金属包括n型功函数金属。