公开(公告)号：US20160196381A1

公开(公告)日：2016-07-07

申请号：US15071890

申请日：2016-03-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang NING ,  Guido UEBERREITER ,  Llyod C. LITT ,  Paul ACKMANN

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/68 ,  G03F7/70441 ,  G03F7/70516 ,  G03F7/70625 ,  G03F7/70683 ,  G06F17/5072

Abstract: A metrology pattern layout for a circuit structure is provided, the metrology pattern layout including a plurality of quadrants, in which quadrants a first wafer measurement pattern, a second wafer measurement pattern, a reticle registration pattern, and a reticle measurement pattern may be arranged to facilitate correlation of reticle metrology data with wafer metrology data. The reticle registration pattern may further include one or more outermost structural elements designed to protect other structural elements within the reticle measurement pattern from being modified in an optical proximity correction process. A method of optical proximity correction process is provided, in which a reticle measurement pattern may be obtained and classified to add or modify a rule set of the optical proximity correction process.