公开(公告)号：US20160254234A1

公开(公告)日：2016-09-01

申请号：US15152600

申请日：2016-05-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jae Kyu CHO ,  Shan GAO

IPC: H01L23/00 ,  H01L23/544 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/562 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/784 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/544 ,  H01L23/585 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for forming a dummy metal structure between dies on a semiconductor wafer and the resulting devices are disclosed. Embodiments may include forming metal interconnection layers extending from a substrate of a semiconductor wafer to a top metal interconnection layer of the semiconductor wafer between a plurality of die regions, each of the metal interconnection layers including a plurality of dummy vertical interconnect accesses (VIAs) and a plurality of dummy metal lines, with the plurality of dummy metal lines laterally connecting the plurality of dummy VIAs within each respective metal interconnection layer, and a plurality of dummy VIAs within a first metal interconnection layer vertically connecting a plurality of dummy metal lines within the first metal interconnection layer to a plurality of dummy metal lines within a second metal interconnection layer, and the second metal interconnection layer being below the first metal interconnection layer.

公开(公告)号：US20160322265A1

公开(公告)日：2016-11-03

申请号：US14700639

申请日：2015-04-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shan GAO ,  Sukeshwar KANNAN

IPC: H01L21/66 ,  G01R31/28 ,  H01L49/02 ,  G01R31/02

CPC classification number: H01L22/14 ,  G01R31/2856 ,  G01R31/2894 ,  G01R31/2896 ,  H01L21/563 ,  H01L22/34 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/15311

Abstract: A methodology and circuitry enabling detection of smaller and early stages of failures in under-fill layers in IC chip assemblies are disclosed. Embodiments include providing a top plate having an upper surface and a lower surface, the lower surface bonded by a bonding material layer to an upper surface of a bottom plate; forming transmitter and receiver asymmetric coupling capacitors between the top plate and the bottom plate; forming a transmission line in the bottom plate connecting elements of the transmitter and receiver asymmetric coupling capacitors in the bottom plate; and detecting a failure in the bonding material layer based, at least in part, on electrical characteristics associated with the transmitter asymmetric coupling capacitor, the receiver asymmetric coupling capacitor, the transmission line or a combination thereof.

Abstract translation: 公开了一种能够检测IC芯片组件中欠填充层的较小和早期故障阶段的方法和电路。 实施例包括提供具有上表面和下表面的顶板，下表面通过粘合材料层粘合到底板的上表面; 在顶板和底板之间形成发射器和接收器不对称耦合电容器; 在底板中的发射机和接收机不对称耦合电容器的底板连接元件中形成传输线; 并且至少部分地基于与发射机非对称耦合电容器，接收器非对称耦合电容器，传输线或其组合相关联的电特性来检测接合材料层中的故障。

公开(公告)号：US20160225679A1

公开(公告)日：2016-08-04

申请号：US14611496

申请日：2015-02-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sukeshwar KANNAN ,  Xiaoqiang ZHANG ,  Shan GAO

IPC: H01L21/66 ,  H01L21/768

CPC classification number: H01L22/14 ,  H01L22/34 ,  H01L23/481 ,  H01L23/5256 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: Methods of testing TSVs using eFuse cells prior to and post bonding wafers in a 3D IC stack are provided. Embodiments include providing a wafer of a 3D IC stack, the wafer having thin and thick metal layers; forming first and second TSVs on the wafer, the first and second TSVs laterally separated; forming an eFuse cell between and separated from the first and second TSVs; forming a FF adjacent to the second TSV and on an opposite side of the second TSV from the eFuse cell; connecting the first TSV, the eFuse cell, the second TSV, and the FF in series in an electric circuit; and testing the first and second TSVs prior to bonding the wafer to a subsequent wafer in the 3D IC stack.

Abstract translation: 提供了在3D IC堆叠中将晶片接合和贴合之后使用eFuse电池测试TSV的方法。 实施例包括提供3D IC堆叠的晶片，该晶片具有薄而厚的金属层; 在晶片上形成第一和第二TSV，第一和第二TSV横向分离; 在第一和第二TSV之间形成eFuse单元并在其间分离; 在第二TSV附近形成与第二TSV相对的FF与eFuse单元; 在电路中串联连接第一TSV，eFuse单元，第二TSV和FF; 以及在将晶片连接到3D IC堆叠中的后续晶片之前测试第一和第二TSV。

公开(公告)号：US20160111360A1

公开(公告)日：2016-04-21

申请号：US14515836

申请日：2014-10-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jae Kyu CHO ,  Shan GAO

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/562 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/784 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/544 ,  H01L23/585 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for forming a dummy metal structure between dies on a semiconductor wafer and the resulting devices are disclosed. Embodiments may include forming metal interconnection layers extending from a substrate of a semiconductor wafer to a top metal interconnection layer of the semiconductor wafer between a plurality of die regions, each of the metal interconnection layers including a plurality of dummy vertical interconnect accesses (VIAs) and a plurality of dummy metal lines, with the plurality of dummy metal lines laterally connecting the plurality of dummy VIAs within each respective metal interconnection layer, and a plurality of dummy VIAs within a first metal interconnection layer vertically connecting a plurality of dummy metal lines within the first metal interconnection layer to a plurality of dummy metal lines within a second metal interconnection layer, and the second metal interconnection layer being below the first metal interconnection layer.

Abstract translation: 公开了在半导体晶片上的管芯之间形成虚设金属结构的方法和所得到的器件。 实施例可以包括在多个管芯区域之间形成从半导体晶片的衬底延伸到半导体晶片的顶部金属互连层的金属互连层，每个金属互连层包括多个虚拟垂直互连访问（VIA）和 多个虚拟金属线，多个虚拟金属线横向连接各个金属互连层内的多个伪VIA，以及在第一金属互连层内垂直连接多个虚拟金属线内的虚拟VIA 第一金属互连层连接到第二金属互连层内的多个虚拟金属线，第二金属互连层位于第一金属互连层的下方。