公开(公告)号：US20150221770A1

公开(公告)日：2015-08-06

申请号：US14686228

申请日：2015-04-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes M. van Meer ,  Michael J. Hargrove ,  Christian Gruensfelder ,  Yanxiang Liu ,  Srikanth B. Samavedam

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1608 ,  H01L29/66795 ,  H01L29/7855

Abstract: Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins.

Abstract translation: 提供了用于在器件（例如，鳍式场效应晶体管器件（FinFET））中实现硅鳍外延生长的方法。 具体地，提供了用于形成用于FinFET器件的一组硅散热片的方法，所述FinFET器件包括：在衬底上形成的一组栅极结构，所述一组栅极结构中的每一个包括覆盖层和一组间隔物; 在该组栅极结构上形成的氧化物填充物; 通过从所述一组或多组所述栅极结构中去除所述覆盖层和所述一组间隔物而在所述器件中形成的一组开口; 外延生长在器件中的开口组内然后平坦化的硅材料; 并且其中蚀刻氧化物填充物以暴露硅材料并形成该组散热片。

公开(公告)号：US09034737B2

公开(公告)日：2015-05-19

申请号：US13956475

申请日：2013-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes M. van Meer ,  Michael J. Hargrove ,  Christian Gruensfelder ,  Yanxiang Liu ,  Srikanth B. Samavedam

IPC: H01L21/20 ,  H01L21/36 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1608 ,  H01L29/66795 ,  H01L29/7855

Abstract: Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins.

Abstract translation: 提供了用于在器件（例如，鳍式场效应晶体管器件（FinFET））中实现硅鳍外延生长的方法。 具体地，提供了用于形成用于FinFET器件的一组硅散热片的方法，所述FinFET器件包括：在衬底上形成的一组栅极结构，所述一组栅极结构中的每一个包括覆盖层和一组间隔物; 在该组栅极结构上形成的氧化物填充物; 通过从所述一组或多组所述栅极结构中去除所述覆盖层和所述一组间隔物而在所述器件中形成的一组开口; 外延生长在器件中的开口组内然后平坦化的硅材料; 并且其中蚀刻氧化物填充物以暴露硅材料并形成该组散热片。

公开(公告)号：US20150050792A1

公开(公告)日：2015-02-19

申请号：US13965258

申请日：2013-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Srikanth B. Samavedam ,  Zhenyu Hu ,  Andy Wei ,  Qi Zhang ,  Nicholas V. LiCausi ,  Daniel Pham

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76224

Abstract: Methods for forming a narrow isolation region are disclosed. The narrow isolation region may serve as an extra narrow diffusion break, suitable for use in 3D FinFET technologies. A pad nitride layer is formed over a semiconductor substrate. A cavity is formed in the pad nitride layer. A conformal spacer liner is deposited in the cavity. An anisotropic etch process then forms a trench in the semiconductor substrate. The trench is narrow enough such that a dummy gate completely covers the trench. Epitaxial stressor regions may then be formed adjacent to the dummy gate. The trench is narrow enough such that there is a gap between the epitaxial stressor regions and the trench.

Abstract translation: 公开了形成窄隔离区域的方法。 狭窄的隔离区域可以用作非常窄的扩散断裂，适用于3D FinFET技术。 在半导体衬底上形成衬垫氮化物层。 在衬垫氮化物层中形成腔体。 在腔中沉积保形间隔衬垫。 然后，各向异性蚀刻工艺在半导体衬底中形成沟槽。 沟槽足够窄，使得虚拟栅极完全覆盖沟槽。 然后可以在与虚拟栅极相邻的位置形成外延应力区域。 沟槽足够窄，使得在外延应力区域和沟槽之间存在间隙。

公开(公告)号：US09437740B2

公开(公告)日：2016-09-06

申请号：US14686228

申请日：2015-04-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes M. van Meer ,  Michael J. Hargrove ,  Christian Gruensfelder ,  Yanxiang Liu ,  Srikanth B. Samavedam

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L29/7856 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1608 ,  H01L29/66795 ,  H01L29/7855

Abstract: Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins.

公开(公告)号：US20150037945A1

公开(公告)日：2015-02-05

申请号：US13956475

申请日：2013-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes M. van Meer ,  Michael J. Hargrove ,  Christian Gruensfelder ,  Yanxiang Liu ,  Srikanth B. Samavedam

IPC: H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1608 ,  H01L29/66795 ,  H01L29/7855

Abstract: Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins.