公开(公告)号：US10262941B2

公开(公告)日：2019-04-16

申请号：US15136384

申请日：2016-04-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jason Eugene Stephens ,  Tuhin Guha Neogi ,  Kai Sun ,  Deniz Elizabeth Civay ,  David Charles Pritchard ,  Andy Wei

IPC: H01L21/33 ,  H01L23/528 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with cross coupled contacts using patterning for cross couple pick-up are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a first lithography to pattern a first shape; performing a second lithography to pattern a second shape overlapping a portion of the first shape; processing the first shape and the second shape to form an isolation region at the overlap; and forming four regions separated by the isolation region. An intermediate semiconductor device is also disclosed.

公开(公告)号：US09583351B2

公开(公告)日：2017-02-28

申请号：US14083604

申请日：2013-11-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Wei

IPC: H01L21/283 ,  H01L29/417 ,  H01L21/768

CPC classification number: H01L21/283 ,  H01L21/76897 ,  H01L29/41791

Abstract: An inverted contact and methods of fabrication are provided. A sacrificial layer is patterned in an inverted trapezoid shape, and oxide is deposited around the pattern. The sacrificial layer is removed, and a metal contact material is deposited, taking an inverted-trapezoid shape. Embodiments of the present invention provide an inverted contact, having a wider base and a narrower top. The wider base provides improved electrical contact to the underlying active area. The narrower top allows for closer placement of adjacent contacts, serving to increase overall circuit density of an integrated circuit.

Abstract translation: 提供反向接触和制造方法。 牺牲层以倒梯形的形状图案化，并且氧化物沉积在图案周围。 去除牺牲层，沉积金属接触材料，呈倒梯形。 本发明的实施例提供了一种具有较宽底座和较窄顶部的倒置接触件。 较宽的基座提供与底层有效区域的改善的电接触。 较窄的顶部允许相邻触点的更靠近放置，用于增加集成电路的总体电路密度。

公开(公告)号：US09520395B2

公开(公告)日：2016-12-13

申请号：US14949481

申请日：2015-11-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Andy Wei ,  Xiang Hu ,  Jerome F. Wandell ,  Sandeep Gaan

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/02 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/02488 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.

Abstract translation: 提供了使用存储层在半导体器件中图案化多个致密特征的方法。 具体地，一种方法包括：在存储层中图形化多个开口; 在所述多个开口的每一个内形成间隙填充材料; 去除记忆层; 去除邻近间隙填充材料的蚀刻停止层，其中蚀刻停止层的一部分保留在间隙填充材料的下面; 蚀刻硬掩模以在所述一组栅极结构之上形成一组开口，其中对所述硬掩模的蚀刻还从所述蚀刻停止层的剩余部分顶部除去所述间隙填充材料; 并蚀刻半导体器件以去除每组开口内的硬掩模。 在一个实施例中，然后通过蚀刻对栅极结构有选择性的电介质层，在半导体器件的一组鳍片上形成一组虚拟S / D接触柱。

公开(公告)号：US09406775B1

公开(公告)日：2016-08-02

申请号：US14696684

申请日：2015-04-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Wei ,  Youngtag Woo

IPC: H01L21/76 ,  H01L29/66 ,  H01L29/78 ,  H01L23/535 ,  H01L27/11 ,  H01L21/768

CPC classification number: H01L29/66515 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/1104 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for forming a self-aligned gate-cut in close proximity to a gate contact and the resulting device are disclosed. Embodiments include providing a substrate with silicon fins and a metal gate with a nitride-cap perpendicular to and over the fins, with source/drain regions, each with an oxide-cap, on the fins on opposite sides of the gate; forming parallel dielectric lines, separated from each other, perpendicular to and over the gate; forming a photoresist over the parallel dielectric lines, forming an opening in the photoresist exposing a nitride-cap between two fins; removing the exposed nitride-cap exposing an underlying metal gate; removing the exposed metal gate and a remainder of the photoresist; forming low-k dielectric lines between the parallel dielectric lines; removing sections of the parallel dielectric lines; forming perpendicular interconnects between the low-k dielectric lines; removing a remainder of the parallel dielectric lines forming trenches; and filling the trenches with metal.

Abstract translation: 公开了用于形成非常接近栅极接触的自对准栅极切割和所得到的器件的方法。 实施例包括：提供具有硅散热片的衬底和金属栅极，其中氮化物帽垂直于翅片和鳍上，源极/漏极区域各自具有氧化物盖，位于栅极的相对侧上的鳍片上; 形成彼此分离的平行介质线，垂直于栅极和栅极上方; 在所述平行介质线上形成光致抗蚀剂，在所述光致抗蚀剂中形成在两个翅片之间暴露氮化物盖的开口; 去除暴露的氮化物盖，暴露下面的金属栅极; 去除暴露的金属栅极和其余的光致抗蚀剂; 在平行介质线之间形成低k介质线; 去除平行介电线路的部分; 在低k介质线之间形成垂直互连; 去除形成沟槽的平行介质线的剩余部分; 并用金属填充沟槽。

公开(公告)号：US09306019B2

公开(公告)日：2016-04-05

申请号：US14457934

申请日：2014-08-12

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jing Wan ,  Guillaume Bouche ,  Andy Wei ,  Shao Ming Koh

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a layered fin overlying a substrate, where the layered fin includes an SiGe layer and an Si layer. The SiGe layer and the Si layer alternate along a height of the layered fin. A dummy gate is formed overlying the substrate and the layered fin, and a source and a drain area formed in contact with the layered fin. The dummy gate is removed to expose the SiGe layer and the Si layer, and the Si layer is removed to produce an SiGe nanowire. A high K dielectric layer that encases the SiGe nanowire between the source and the drain is formed, and a replacement metal gate is formed so that the replacement metal gate encases the high K dielectric layer and the SiGe nanowire between the source and drain.

Abstract translation: 提供了集成电路及其制造方法。 一种集成电路的制造方法，其特征在于，形成覆盖基板的分层散热片，其中层状散热片包括SiGe层和Si层。 SiGe层和Si层沿着层状翅片的高度交替。 形成覆盖基板和分层翅片的虚拟栅极以及与层状翅片接触形成的源极和漏极区域。 去除伪栅极以暴露SiGe层和Si层，并且去除Si层以产生SiGe纳米线。 形成在源极和漏极之间封装SiGe纳米线的高K电介质层，并且形成替代金属栅极，使得替代金属栅极包围源极和漏极之间的高K电介质层和SiGe纳米线。

公开(公告)号：US20160079242A1

公开(公告)日：2016-03-17

申请号：US14949481

申请日：2015-11-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： GUILLAUME BOUCHE ,  Andy Wei ,  Xiang Hu ,  Jerome F. Wandell ,  Sandeep Gaan

IPC: H01L27/088 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/02488 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.

公开(公告)号：US09123568B2

公开(公告)日：2015-09-01

申请号：US14086563

申请日：2013-11-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Richard Carter ,  Andy Wei

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L23/485 ,  H01L23/28

CPC classification number: H01L27/092 ,  H01L21/28512 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/28 ,  H01L23/485 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7847 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of NMOS transistor elements, each including a first gate electrode structure above a first active region, at least two of the plurality of first gate electrode structures including a first encapsulating stack having a first dielectric cap layer and a first sidewall spacer stack. The semiconductor device also includes a plurality of PMOS transistor elements, each including a second gate electrode structure above a second active region, wherein at least two of the plurality of second gate electrode structures include a second encapsulating stack having a second dielectric cap layer and a second sidewall spacer stack. Additionally, the first and second sidewall spacer stacks each include at least three dielectric material layers, wherein each of the three dielectric material layers of the first and second sidewall spacer stacks include the same dielectric material.

Abstract translation: 半导体器件包括多个NMOS晶体管元件，每个NMOS晶体管元件均包括在第一有源区上方的第一栅极电极结构，多个第一栅电极结构中的至少两个包括第一封装堆叠，第一封装堆叠具有第一电介质盖层和第一侧壁 间隔堆叠 半导体器件还包括多个PMOS晶体管元件，每个PMOS晶体管元件包括在第二有源区上方的第二栅极电极结构，其中多个第二栅电极结构中的至少两个包括具有第二电介质盖层和 第二侧壁间隔堆叠。 另外，第一和第二侧壁间隔堆叠每个包括至少三个介电材料层，其中第一和第二侧壁间隔物叠层的三个介电材料层中的每一个包括相同的电介质材料。

公开(公告)号：US20150214113A1

公开(公告)日：2015-07-30

申请号：US14164582

申请日：2014-01-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Guillaume Bouche ,  Erik Geiss ,  Scott Beasor ,  Andy Wei ,  Deniz Elizabeth Civay

IPC: H01L21/8234 ,  H01L29/16 ,  H01L21/311 ,  H01L21/027 ,  H01L21/768 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L21/823431 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/485 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/785

Abstract: A method for fabricating a finFET integrated circuit includes providing a finFET integrated circuit structure including a fin structure, a replacement metal gate structure having a silicon nitride cap disposed over and in contact with the fin structure, a contact structure including a tungsten material also disposed over and in contact with the fin structure, and an insulating layer disposed over the replacement metal gate structure and the contact structure. The method further includes forming a first opening in the insulating layer over the replacement gate structure and a second opening in the insulating layer over the contact structure. Forming the first and second openings includes exposing the FinFET integrated circuit structure to a single extreme ultraviolet lithography patterning. Still further, the method includes removing a portion of the silicon nitride material of the replacement metal gate structure and forming a metal fill material in the first and second openings.

Abstract translation: 一种用于制造finFET集成电路的方法包括提供finFET集成电路结构，其包括翅片结构，具有设置在翅片结构上并与翅片结构接触的氮化硅盖的替换金属栅极结构，包括钨材料的接触结构也布置在 并且与翅片结构接触，以及设置在替换金属栅极结构和接触结构之上的绝缘层。 所述方法还包括在所述绝缘层上形成位于所述替代栅极结构上的第一开口和在所述接触结构上的所述绝缘层中的第二开口。 形成第一和第二开口包括将FinFET集成电路结构暴露于单个极紫外光刻图案。 此外，该方法包括去除替代金属栅极结构的一部分氮化硅材料并在第一和第二开口中形成金属填充材料。

公开(公告)号：US20140220759A1

公开(公告)日：2014-08-07

申请号：US14244611

申请日：2014-04-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thilo Scheiper ,  Stefan Flachowsky ,  Andy Wei

IPC: H01L29/66 ,  H01L21/762

CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L21/76895 ,  H01L21/76897

Abstract: Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes forming a dummy gate structure including a dummy gate electrode having sidewalls and overlying a semiconductor substrate and first and second sidewall spacers on the sidewalls of the dummy gate electrode. The method includes removing the dummy gate electrode to form a trench bounded by the first and second sidewall spacers. The method removes an upper portion of the first sidewall spacer and deposits a layer of metal in the trench and over a remaining portion of the first sidewall spacer to form a gate electrode and an interconnect.

Abstract translation: 提供了用于制造包括门到活动触点的集成电路的方法。 一种方法包括形成虚拟栅极结构，其包括具有侧壁并覆盖半导体衬底的伪栅极电极以及虚设栅电极的侧壁上的第一和第二侧壁间隔物。 该方法包括去除伪栅电极以形成由第一和第二侧壁间隔物限定的沟槽。 该方法移除第一侧壁间隔物的上部，并将一层金属沉积在沟槽中并在第一侧壁间隔物的剩余部分上方形成栅电极和互连。

公开(公告)号：US08742513B2

公开(公告)日：2014-06-03

申请号：US13628468

申请日：2012-09-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Wei ,  Andrew Waite

IPC: H01L27/11

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823842 ,  H01L27/0629 ,  H01L28/20

Abstract: In a semiconductor device comprising sophisticated high-k metal gate structures formed in accordance with a replacement gate approach, semiconductor-based resistors may be formed above isolation structures substantially without being influenced by the replacement gate approach. Consequently, enhanced area efficiency may be achieved compared to conventional strategies, in which the resistive structures may have to be provided on the basis of a gate electrode metal, while, nevertheless, a low parasitic capacitance may be accomplished due to providing the resistive structures above the isolation structure.

Abstract translation: 在包括根据替换栅极方法形成的复杂的高k金属栅极结构的半导体器件中，半导体基电阻器可以基本上不受更换栅极方法的影响而形成在隔离结构之上。 因此，与常规策略相比，可以实现增强的面积效率，其中电阻结构可能必须基于栅电极金属提供，而尽管如此，可以通过提供上述电阻结构来实现低寄生电容 隔离结构。