公开(公告)号：US20140264486A1

公开(公告)日：2014-09-18

申请号：US13839626

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel Pham ,  Xiuyu Cai ,  Balasubramanian Pranatharthiharan ,  Pranita Kulkarni

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/4232 ,  H01L21/28247 ,  H01L29/66545 ,  H01L29/78

Abstract: One method includes forming a recessed gate/spacer structure that partially defines a spacer/gate cap recess, forming a gate cap layer in the spacer/gate cap recess, forming a gate cap protection layer on an upper surface of the gate cap layer, and removing portions of the gate cap protection layer, leaving a portion of the gate cap protection layer positioned on the upper surface of the gate cap layer. A device disclosed herein includes a gate/spacer structure positioned in a layer of insulating material, a gate cap layer positioned on the gate/spacer structure, wherein sidewalls of the gate cap layer contact the layer of insulating material, and a gate cap protection layer positioned on an upper surface of the gate cap layer, wherein the sidewalls of the gate cap protection layer also contact the layer of insulating material.

Abstract translation: 一种方法包括形成凹入的栅极/间隔结构，其部分地限定间隔物/栅极盖凹部，在间隔物/栅极盖凹部中形成栅极盖层，在栅极盖层的上表面上形成栅极盖保护层，以及 去除栅极帽保护层的部分，留下栅极盖保护层的一部分位于栅极盖层的上表面上。 本文公开的装置包括定位在绝缘材料层中的栅极/间隔结构，位于栅极/间隔物结构上的栅极盖层，其中栅极盖层的侧壁接触绝缘材料层，栅极盖保护层 定位在栅极盖层的上表面上，其中栅极盖保护层的侧壁也接触绝缘材料层。

公开(公告)号：US09219002B2

公开(公告)日：2015-12-22

申请号：US14028724

申请日：2013-09-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhenyu Hu ,  Andy Wei ,  Qi Zhang ,  Richard J. Carter ,  Hongliang Shen ,  Daniel Pham ,  Sruthi Muralidharan

IPC: H01L21/336 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/76224 ,  H01L21/3081 ,  H01L21/845 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide deposited in a set of openings formed through the pad layer and into the substrate, a mandrel layer deposited over the oxide material and the pad layer, and a set of fins patterned in the IC device without etching the alignment and overlay mark. With this approach, the alignment and overlay mark is provided with the fin cut (FC) layer and, therefore, avoids finification.

Abstract translation: 提供了用于提高集成电路（IC）设备的覆盖性能的方法。 具体地，IC器件（例如，鳍式场效应晶体管（FinFET））设置有形成在衬底上的氧化物层和衬垫层，其中氧化物层包括取向和覆盖标记，沉积在一组 通过衬垫层并进入衬底形成的开口，沉积在氧化物材料和衬垫层上的心轴层，以及在IC器件中图案化的一组鳍片，而不蚀刻对准和重叠标记。 利用这种方法，对准和重叠标记设置有翅片切割（FC）层，因此避免了精细化。

公开(公告)号：US08846491B1

公开(公告)日：2014-09-30

申请号：US13921377

申请日：2013-06-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel Pham ,  Zhenyu Hu ,  Andy Wei ,  Nicholas V. LiCausi

IPC: H01L21/76 ,  H01L29/78 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L29/785 ,  H01L21/02104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795

Abstract: Embodiments herein provide approaches for forming a diffusion break during a replacement metal gate process. Specifically, a semiconductor device is provided with a set of replacement metal gate (RMG) structures over a set of fins patterned from a substrate; a dielectric material over an epitaxial junction area; an opening formed between the set of RMG structures and through the set of fins, wherein the opening extends through the dielectric material, the expitaxial junction area, and into the substrate; and silicon nitride (SiN) deposited within the opening to form the diffusion break.

Abstract translation: 本文的实施例提供了在替换金属浇口工艺期间形成扩散断裂的方法。 具体而言，半导体器件在从衬底图案化的一组鳍片上设置有一组置换金属栅极（RMG）结构; 在外延结区上的电介质材料; 所述开口形成在所述一组RMG结构之间并且穿过所述一组翅片，其中所述开口延伸穿过所述电介质材料，所述外延结结区域并进入所述基板; 和沉积在开口内的氮化硅（SiN）以形成扩散断裂。

公开(公告)号：US08871582B2

公开(公告)日：2014-10-28

申请号：US13839626

申请日：2013-03-15

Applicant: GlobalFoundries Inc. ,  International Business Machines Corporation

Inventor： Daniel Pham ,  Xiuyu Cai ,  Balasubramanian Pranatharthiharan ,  Pranita Kulkarni

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/4232 ,  H01L21/28247 ,  H01L29/66545 ,  H01L29/78

Abstract: One method includes forming a recessed gate/spacer structure that partially defines a spacer/gate cap recess, forming a gate cap layer in the spacer/gate cap recess, forming a gate cap protection layer on an upper surface of the gate cap layer, and removing portions of the gate cap protection layer, leaving a portion of the gate cap protection layer positioned on the upper surface of the gate cap layer. A device disclosed herein includes a gate/spacer structure positioned in a layer of insulating material, a gate cap layer positioned on the gate/spacer structure, wherein sidewalls of the gate cap layer contact the layer of insulating material, and a gate cap protection layer positioned on an upper surface of the gate cap layer, wherein the sidewalls of the gate cap protection layer also contact the layer of insulating material.

Abstract translation: 一种方法包括形成凹入的栅极/间隔结构，其部分地限定间隔物/栅极盖凹部，在间隔物/栅极盖凹部中形成栅极盖层，在栅极盖层的上表面上形成栅极盖保护层，以及 去除栅极帽保护层的部分，留下栅极盖保护层的一部分位于栅极盖层的上表面上。 本文公开的装置包括定位在绝缘材料层中的栅极/间隔结构，位于栅极/间隔物结构上的栅极盖层，其中栅极盖层的侧壁接触绝缘材料层，栅极盖保护层 定位在栅极盖层的上表面上，其中栅极盖保护层的侧壁也接触绝缘材料层。

公开(公告)号：US20140264487A1

公开(公告)日：2014-09-18

申请号：US13839802

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel Pham ,  Xiuyu Cai ,  Balasubramanian Pranatharthiharan ,  Pranita Kulkarni

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42364 ,  H01L21/28247 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78

Abstract: One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material.

Abstract translation: 本文公开的一种方法包括形成封装并保护栅极盖层的第一和第二栅极盖保护层。 本文公开的新型晶体管器件包括位于半导体衬底上方的栅极结构，邻近栅极结构定位的间隔结构，位于衬底上方并围绕间隔结构的绝缘材料层，位于栅极结构之上的栅极盖层， 所述间隔结构以及封装所述栅极盖层的栅极帽保护材料，其中所述栅极盖保护材料的部分位于所述栅极盖层和所述栅极结构之间，所述间隔物结构和所述绝缘材料层。

公开(公告)号：US09064801B1

公开(公告)日：2015-06-23

申请号：US14161721

申请日：2014-01-23

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  Samsung Electronics Co., Ltd.

Inventor： David V. Horak ,  Jin Wook Lee ,  Daniel Pham ,  Shom S. Ponoth ,  Balasubramanian Pranatharthiharan

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/51 ,  H01L21/283

CPC classification number: H01L21/283 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

Abstract: A method of forming a semiconductor structure includes forming a metal gate above a semiconductor substrate and gate spacers adjacent to the metal gate surrounded by an interlevel dielectric (ILD) layer. The gate spacers and the metal gate are recessed until a height of the metal gate is less than a height of the gate spacers. An etch stop liner is deposited above the gate spacers and the metal gate. A gate cap is deposited above the etch stop liner to form a bi-layer gate cap. A contact hole is formed in the ILD layer adjacent to the metal gate, the etch stop liner in the bi-layer gate cap prevents damage of the gate spacers during formation of the contact hole. A conductive material is deposited in the contact hole to form a contact to a source-drain region in the semiconductor substrate.

Abstract translation: 形成半导体结构的方法包括在半导体衬底之上形成金属栅极和邻近由层间电介质（ILD）层围绕的金属栅极的栅极间隔。 栅极间隔物和金属栅极凹入直到金属栅极的高度小于栅极间隔物的高度。 蚀刻停止衬垫沉积在栅极间隔物和金属栅极上方。 栅极盖沉积在蚀刻停止衬垫上方以形成双层栅极盖。 在与金属栅极相邻的ILD层中形成接触孔，双层栅极帽中的蚀刻停止衬垫防止在形成接触孔期间损坏栅极间隔物。 导电材料沉积在接触孔中以与半导体衬底中的源极 - 漏极区形成接触。

公开(公告)号：US20150041869A1

公开(公告)日：2015-02-12

申请号：US14526126

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Daniel Pham ,  Xiuyu Cai ,  Balasubramanian Pranatharthiharan ,  Pranita Kulkarni

IPC: H01L29/423 ,  H01L29/51

CPC classification number: H01L29/42364 ,  H01L21/28247 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78

Abstract: One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material.

Abstract translation: 本文公开的一种方法包括形成封装并保护栅极盖层的第一和第二栅极盖保护层。 本文公开的新型晶体管器件包括位于半导体衬底上方的栅极结构，邻近栅极结构定位的间隔结构，位于衬底上方并围绕间隔结构的绝缘材料层，位于栅极结构之上的栅极盖层， 所述间隔结构以及封装所述栅极盖层的栅极帽保护材料，其中所述栅极盖保护材料的部分位于所述栅极盖层和所述栅极结构之间，所述间隔物结构和所述绝缘材料层。

公开(公告)号：US08906754B2

公开(公告)日：2014-12-09

申请号：US13839802

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Daniel Pham ,  Xiuyu Cai ,  Balasubramanian Pranatharthiharan ,  Pranita Kulkarni

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42364 ,  H01L21/28247 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78

Abstract: One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material.

Abstract translation: 本文公开的一种方法包括形成封装并保护栅极盖层的第一和第二栅极盖保护层。 本文公开的新型晶体管器件包括位于半导体衬底上方的栅极结构，邻近栅极结构定位的间隔结构，位于衬底上方并围绕间隔结构的绝缘材料层，位于栅极结构之上的栅极盖层， 所述间隔结构以及封装所述栅极盖层的栅极帽保护材料，其中所述栅极盖保护材料的部分位于所述栅极盖层和所述栅极结构之间，所述间隔物结构和所述绝缘材料层。

公开(公告)号：US09419137B1

公开(公告)日：2016-08-16

申请号：US14641809

申请日：2015-03-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Abner Bello ,  Xiuyu Cai ,  Hugh Porter ,  Daniel Pham

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/324 ,  H01L21/3105 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/7847 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924

Abstract: A method of straining fins of a FinFET device by using a stress memorization film and the resulting device are provided. Embodiments include providing a plurality of bulk Si fins, the plurality of bulk Si fins having a recessed oxide layer therebetween; forming a stress memorization layer over the plurality of bulk Si fins and the recessed oxide layer; annealing the stress memorization layer, the plurality of bulk Si fins, and the recessed oxide layer; and removing the stress memorization layer.

Abstract translation: 提供了通过使用应力记忆膜来制造FinFET器件的鳍片的方法以及所得到的器件。 实施例包括提供多个体积Si散热片，所述多个本体Si散热片在其间具有凹陷的氧化物层; 在所述多个体积Si散热片和所述凹陷氧化物层上形成应力记忆层; 退火应力记忆层，多个体积Si散热片和凹陷氧化物层; 并去除应力记忆层。

公开(公告)号：US09263537B2

公开(公告)日：2016-02-16

申请号：US14526126

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Daniel Pham ,  Xiuyu Cai ,  Balasubramanian Pranatharthiharan ,  Pranita Kulkarni

IPC: H01L21/70 ,  H01L29/423 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/42364 ,  H01L21/28247 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78

Abstract: One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material.

Abstract translation: 本文公开的一种方法包括形成封装并保护栅极盖层的第一和第二栅极盖保护层。 本文公开的新型晶体管器件包括位于半导体衬底上方的栅极结构，邻近栅极结构定位的间隔结构，位于衬底上方并围绕间隔结构的绝缘材料层，位于栅极结构之上的栅极盖层， 所述间隔结构以及封装所述栅极盖层的栅极帽保护材料，其中所述栅极盖保护材料的部分位于所述栅极盖层和所述栅极结构之间，所述间隔物结构和所述绝缘材料层。