公开(公告)号：US20210013095A1

公开(公告)日：2021-01-14

申请号：US16504737

申请日：2019-07-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xuan Anh Tran ,  Eswar Ramanathan ,  Sunil Kumar Singh ,  Suryanarayana Kalaga ,  Suresh Kumar Regonda ,  Juan Boon Tan

IPC: H01L21/768 ,  H01L23/535

Abstract: One illustrative method disclosed herein includes, among other things, selectively forming a sacrificial material on an upper surface of a top electrode of a memory cell, forming at least one layer of insulating material around the sacrificial material and removing the sacrificial material so as to form an opening in the at least one layer of insulating material, wherein the opening exposes the upper surface of the top electrode. The method also includes forming an internal sidewall spacer within the opening in the at least one layer of insulating material and forming a conductive contact structure that is conductively coupled to the upper surface of the top electrode, wherein a portion of the conductive contact structure is surrounded by the internal sidewall spacer.

公开(公告)号：US09741853B2

公开(公告)日：2017-08-22

申请号：US14926897

申请日：2015-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mantavya Sinha ,  Prasanna Kannan ,  Cuiqin Xu ,  Tao Wang ,  Suresh Kumar Regonda

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324

CPC classification number: H01L29/7848 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/283 ,  H01L21/324 ,  H01L29/66477 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7847

Abstract: Disclosed are methods for stress memorization techniques and transistor devices prepared by such methods. In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate having a channel region underlying, at least partially, the gate structure, the fabricating involving: performing a nitrogen ion implantation process by implanting nitrogen ions into the substrate to thereby form a stress region in the substrate, the stress region separated by the channel region, wherein the stress region has a stress region depth; forming a capping material layer above the NMOS transistor device; and, with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the stress region. In another embodiment, an amorphization ion implantation is performed prior to, after or along with the nitrogen ion implantation.