公开(公告)号：US10290634B2

公开(公告)日：2019-05-14

申请号：US15001903

申请日：2016-01-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wen Pin Peng ,  Min-hwa Chi

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/306 ,  H01L21/8234

Abstract: A multi-Vt FinFET includes a semiconductor substrate, multiple first fins coupled to the semiconductor substrate having a first fin pitch, and multiple second fins coupled to the semiconductor substrate having a second fin pitch larger than the first fin pitch. The semiconductor structure further includes transistor(s) on the multiple first fins, and transistor(s) on the multiple second fins, a threshold voltage of the transistor(s) on the multiple second fins being higher than that of the transistor(s) on the multiple first fins.

公开(公告)号：US20170069547A1

公开(公告)日：2017-03-09

申请号：US14845543

申请日：2015-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wen Pin Peng ,  Min-hwa Chi ,  Garo Jacques Derderian

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/823864 ,  H01L21/0206 ,  H01L21/02252 ,  H01L21/0234 ,  H01L21/31111 ,  H01L21/823814 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/78

Abstract: Disclosed herein is a method of forming a CMOS integrated circuit product (comprised of first and second opposite type transistors) that includes forming a first spacer proximate both the first and second gate structures, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, and forming first raised epi semiconductor material source/drain regions for the first transistor. Thereafter, performing a first surface oxidation process so as to selectively form a hydrophilic material on exposed surfaces of the first raised epi semiconductor material and performing an etching process on both the transistors so as to remove the initial second spacer and the layer of second spacer material.

Abstract translation: 本文公开了一种形成CMOS集成电路产品（由第一和第二相对型晶体管组成）的方法，其包括形成靠近第一和第二栅极结构的第一间隔物，形成靠近第一晶体管的第一间隔物的初始第二间隔物 以及在所述第二晶体管上方的第二间隔物层，以及为所述第一晶体管形成第一凸起的外延半导体材料源极/漏极区。 此后，进行第一表面氧化处理，以在第一隆起的外延半导体材料的暴露表面上选择性地形成亲水材料，并在两个晶体管上执行蚀刻处理，以去除初始的第二间隔物和第二间隔物材料层 。

公开(公告)号：US09704759B2

公开(公告)日：2017-07-11

申请号：US14845543

申请日：2015-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wen Pin Peng ,  Min-hwa Chi ,  Garo Jacques Derderian

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/823864 ,  H01L21/0206 ,  H01L21/02252 ,  H01L21/0234 ,  H01L21/31111 ,  H01L21/823814 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/78

Abstract: Disclosed herein is a method of forming a CMOS integrated circuit product (comprised of first and second opposite type transistors) that includes forming a first spacer proximate both the first and second gate structures, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, and forming first raised epi semiconductor material source/drain regions for the first transistor. Thereafter, performing a first surface oxidation process so as to selectively form a hydrophilic material on exposed surfaces of the first raised epi semiconductor material and performing an etching process on both the transistors so as to remove the initial second spacer and the layer of second spacer material.

公开(公告)号：US09385124B1

公开(公告)日：2016-07-05

申请号：US14845499

申请日：2015-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wen Pin Peng ,  Min-hwa Chi ,  Garo Jacques Derderian

IPC: H01L21/336 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L27/092 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

Abstract: One method disclosed herein includes, among other things, forming a first spacer proximate gate structures of first and second transistors that are opposite type transistors, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, performing a timed, wet etching process on both of the transistors so as to completely remove the layer of second spacer material from the second transistor while leaving a reduced thickness second spacer positioned adjacent the first spacer of the first transistor, wherein the reduced thickness second spacer has a thickness that is less than an initial thickness of the initial second spacer, and forming a third spacer on and in contact with the first spacer of the second transistor.

Abstract translation: 本文公开的一种方法包括形成与第一和第二晶体管相对的第一和第二晶体管的栅极结构的第一间隔区，与第一晶体管相反，形成靠近第一晶体管的第一间隔物的初始第二间隔区， 第二晶体管，对两个晶体管执行定时湿式蚀刻处理，以便从第二晶体管完全去除第二间隔物材料层，同时留下邻近第一晶体管的第一间隔物定位的减小厚度的第二间隔物，其中减少 厚度第二间隔物的厚度小于初始第二间隔物的初始厚度，并且在第二晶体管的第一间隔物上形成第三间隔物并与第二间隔物接触。