公开(公告)号：US11264382B2

公开(公告)日：2022-03-01

申请号：US16942816

申请日：2020-07-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jiehui Shu ,  Bharat V. Krishnan

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8234

Abstract: Disclosed are a method of forming a fin-type field effect transistor (FINFET) and a FINFET structure. In the method, isolation regions are formed on opposing sides of a semiconductor fin. Each isolation region is shorter than the fin, has a lower isolation portion adjacent to a lower fin portion, and has an upper isolation portion that is narrower than the lower isolation portion and separated from a bottom section of an upper fin portion by a space. Surface oxidation of the upper fin portion thins the top section, but leaves the bottom section relatively wide. During gate formation, the gate dielectric layer fills the spaces between the bottom section of the upper fin portion and the adjacent isolation regions. Thus, the gate conductor layer is formed above any fin bulge area and degradation of gate control over the channel region due to a non-uniform fin width is minimized or avoided.

公开(公告)号：US11094598B2

公开(公告)日：2021-08-17

申请号：US16508815

申请日：2019-07-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Bharat V. Krishnan ,  Rinus Tek Po Lee ,  Jiehui Shu ,  Hyung Yoon Choi

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/67 ,  H01L29/49

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to multiple threshold voltage devices and methods of manufacture. The structure includes: a gate dielectric material; a gate material on the gate dielectric material, the gate material comprising different thickness in different regions each of which are structured for devices having a different Vt; and a workfunction material on the gate material.