公开(公告)号：US11094598B2

公开(公告)日：2021-08-17

申请号：US16508815

申请日：2019-07-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Bharat V. Krishnan ,  Rinus Tek Po Lee ,  Jiehui Shu ,  Hyung Yoon Choi

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/67 ,  H01L29/49

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to multiple threshold voltage devices and methods of manufacture. The structure includes: a gate dielectric material; a gate material on the gate dielectric material, the gate material comprising different thickness in different regions each of which are structured for devices having a different Vt; and a workfunction material on the gate material.

公开(公告)号：US11362178B2

公开(公告)日：2022-06-14

申请号：US16676488

申请日：2019-11-07

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Jiehui Shu ,  Rinus Tek Po Lee ,  Baofu Zhu

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L27/088

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to asymmetric source and drain structures and methods of manufacture. The structure includes: at least one gate structure; a straight spacer adjacent to the at least one gate structure; and an L-shaped spacer on a side of the at least one gate structure opposing the straight spacer, the L-shaped spacer extending a first diffusion region further away from the at least one gate structure than the straight spacer extends a second diffusion region on a second side away from the at least one gate structure.

公开(公告)号：US11145716B1

公开(公告)日：2021-10-12

申请号：US16877510

申请日：2020-05-19

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Rinus Tek Po Lee ,  Jiehui Shu

IPC: H01L21/02 ,  H01L21/3205 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/786

Abstract: A structure comprises a substrate and a first gate structure and a second gate structure in a dielectric layer over the substrate. The first and second gate structures having a width, the width of the first gate structure is shorter than the width of the second gate structure. The first gate structure comprises a first gate conductor layer and the second gate structure comprises a second gate conductor layer. The first gate conductor layer is made of a different metal from the second gate conductor layer.

公开(公告)号：US11004953B2

公开(公告)日：2021-05-11

申请号：US16454016

申请日：2019-06-26

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Rinus Tek Po Lee ,  Hui Zang ,  Jiehui Shu ,  Hong Yu ,  Wei Hong

IPC: H01L29/66 ,  H01L21/8234

Abstract: A method is provided for fabricating a semiconductor device structure with a short channel and long channel component having different gate dielectric layers without using lithography processes or masks. The method includes forming first and second openings having sidewalls and bottom surfaces in a dielectric layer, the first opening being narrower than the second opening. A first material layer is formed in the first and second openings. A protective layer is formed over the first material layer, wherein the protective layer covers the sidewalls and the bottom surface of the second opening. A block layer is formed to fill the second opening and cover the protective layer therein. The method further includes removing side portions of the protective layer to expose upper portions of the first material layer in the second opening. The block layer is removed from the second opening to expose the protective layer remaining in the second opening. A second material layer is formed over the first material layer on the exposed upper portions of the first material layer in the second opening. An intermix layer is formed in the second opening using the first and second material layers. The protective layer from the second opening is removed to expose the first material layer.