公开(公告)号：US11195947B2

公开(公告)日：2021-12-07

申请号：US16662276

申请日：2019-10-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jagar Singh ,  Luigi Pantisano ,  Anvitha Shampur ,  Frank Scott Johnson ,  Srikanth Balaji Samavedam

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L21/761 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/06

Abstract: A semiconductor device is disclosed including a semiconductor layer, a first well doped with dopants of a first conductivity type defined in the semiconductor layer, a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the semiconductor layer adjacent the first well to define a PN junction between the first and second wells, and an isolation structure positioned in the second well. The semiconductor device also includes a first source/drain region positioned in the first well, a second source/drain region positioned in the second well adjacent a first side of the isolation structure, a doped region positioned in the second well adjacent a second side of the isolation structure, and a gate structure positioned above the semiconductor layer, wherein the gate structure vertically overlaps a portion of the doped region.

公开(公告)号：US11011303B2

公开(公告)日：2021-05-18

申请号：US16106162

申请日：2018-08-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Tung-Hsing Lee ,  Roderick A Augur ,  Siva R K Dangeti ,  Alexander L. Martin ,  Anvitha Shampur

IPC: H01F5/00 ,  H01F27/34 ,  H01L49/02 ,  H01F27/28 ,  H01F41/04 ,  H01F41/12 ,  H01F27/32

Abstract: A dummy fill element for positioning inside an active inductor component of an integrated circuit (IC), the inductor component, the IC and a related method, are disclosed. The active inductor component is configured to convert electrical energy into magnetic energy to reduce parasitic capacitance in an IC. The dummy fill element includes: a first conductive incomplete loop having a first end and a second end, and a second conductive incomplete loop having a first end and a second end. First ends of the first and second conductive incomplete loops are electrically connected, and the second ends of the first and second conductive incomplete loops are electrically connected. In this manner, eddy currents created in each conductive incomplete loop by the magnetic energy cancel at least a portion of each other, allowing for a desired metal fill density and maintaining the inductor's Q-factor.

公开(公告)号：US11610839B2

公开(公告)日：2023-03-21

申请号：US16666808

申请日：2019-10-29

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Tung-Hsing Lee ,  Teng-Yin Lin ,  Frank W. Mont ,  Edward J. Gordon ,  Asmaa Elkadi ,  Alexander Martin ,  Won Suk Lee ,  Anvitha Shampur

IPC: H01L23/522 ,  H01L49/02 ,  H01F27/28 ,  H01F27/24 ,  H01F41/04

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dummy fill structures and methods of manufacture. The structure includes: a passive device formed in interlevel dielectric material; and a plurality of metal dummy fill structures composed of at least one main branch and two extending legs from at least one side of the main branch, the at least two extending legs being positioned and structured to suppress eddy currents of the passive device.

公开(公告)号：US20210126126A1

公开(公告)日：2021-04-29

申请号：US16662276

申请日：2019-10-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jagar Singh ,  Luigi Pantisano ,  Anvitha Shampur ,  Frank Scott Johnson ,  Srikanth Balaji Samavedam

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

Abstract: A semiconductor device is disclosed including a semiconductor layer, a first well doped with dopants of a first conductivity type defined in the semiconductor layer, a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the semiconductor layer adjacent the first well to define a PN junction between the first and second wells, and an isolation structure positioned in the second well. The semiconductor device also includes a first source/drain region positioned in the first well, a second source/drain region positioned in the second well adjacent a first side of the isolation structure, a doped region positioned in the second well adjacent a second side of the isolation structure, and a gate structure positioned above the semiconductor layer, wherein the gate structure vertically overlaps a portion of the doped region.