公开(公告)号：US11289474B2

公开(公告)日：2022-03-29

申请号：US16853137

申请日：2020-04-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Man Gu ,  Wang Zheng ,  Teng-Yin Lin ,  Halting Wang ,  Tung-Hsing Lee

IPC: H01L21/00 ,  H01L27/11 ,  H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L23/66 ,  H01P3/06

Abstract: Structures including a passive device and methods of forming such structures. Multiple fins are positioned on a substrate, and an interconnect structure is positioned over the substrate. The fins contain a polycrystalline semiconductor material, and the interconnect structure includes a passive device that is positioned over the fins. The passive device may be, for example, an inductor or a transmission line.

公开(公告)号：US20210327872A1

公开(公告)日：2021-10-21

申请号：US16853137

申请日：2020-04-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Man Gu ,  Wang Zheng ,  Teng-Yin Lin ,  Haiting Wang ,  Tung-Hsing Lee

IPC: H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L23/66 ,  H01P3/06

Abstract: Structures including a passive device and methods of forming such structures. Multiple fins are positioned on a substrate, and an interconnect structure is positioned over the substrate. The fins contain a polycrystalline semiconductor material, and the interconnect structure includes a passive device that is positioned over the fins. The passive device may be, for example, an inductor or a transmission line.

公开(公告)号：US20210273061A1

公开(公告)日：2021-09-02

申请号：US16803711

申请日：2020-02-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Tamilmani Ethirajan ,  Zhenyu Hu ,  Tung-Hsing Lee

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/73

Abstract: One illustrative device disclosed herein includes a semiconductor substrate and a bipolar junction transistor (BJT) device that comprises a collector region, a base region and an emitter region. In this example, the device also includes a field effect transistor and at least one base conductive contact structure that conductively and physically contacts the base region.

公开(公告)号：US11610839B2

公开(公告)日：2023-03-21

申请号：US16666808

申请日：2019-10-29

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Tung-Hsing Lee ,  Teng-Yin Lin ,  Frank W. Mont ,  Edward J. Gordon ,  Asmaa Elkadi ,  Alexander Martin ,  Won Suk Lee ,  Anvitha Shampur

IPC: H01L23/522 ,  H01L49/02 ,  H01F27/28 ,  H01F27/24 ,  H01F41/04

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dummy fill structures and methods of manufacture. The structure includes: a passive device formed in interlevel dielectric material; and a plurality of metal dummy fill structures composed of at least one main branch and two extending legs from at least one side of the main branch, the at least two extending legs being positioned and structured to suppress eddy currents of the passive device.

公开(公告)号：US11264470B2

公开(公告)日：2022-03-01

申请号：US16803711

申请日：2020-02-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Tamilmani Ethirajan ,  Zhenyu Hu ,  Tung-Hsing Lee

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/73 ,  H01L29/10 ,  H01L29/423

Abstract: One illustrative device disclosed herein includes a semiconductor substrate and a bipolar junction transistor (BJT) device that comprises a collector region, a base region and an emitter region. In this example, the device also includes a field effect transistor and at least one base conductive contact structure that conductively and physically contacts the base region.

公开(公告)号：US11011303B2

公开(公告)日：2021-05-18

申请号：US16106162

申请日：2018-08-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Tung-Hsing Lee ,  Roderick A Augur ,  Siva R K Dangeti ,  Alexander L. Martin ,  Anvitha Shampur

IPC: H01F5/00 ,  H01F27/34 ,  H01L49/02 ,  H01F27/28 ,  H01F41/04 ,  H01F41/12 ,  H01F27/32

Abstract: A dummy fill element for positioning inside an active inductor component of an integrated circuit (IC), the inductor component, the IC and a related method, are disclosed. The active inductor component is configured to convert electrical energy into magnetic energy to reduce parasitic capacitance in an IC. The dummy fill element includes: a first conductive incomplete loop having a first end and a second end, and a second conductive incomplete loop having a first end and a second end. First ends of the first and second conductive incomplete loops are electrically connected, and the second ends of the first and second conductive incomplete loops are electrically connected. In this manner, eddy currents created in each conductive incomplete loop by the magnetic energy cancel at least a portion of each other, allowing for a desired metal fill density and maintaining the inductor's Q-factor.