公开(公告)号：US11848324B2

公开(公告)日：2023-12-19

申请号：US17483104

申请日：2021-09-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ephrem G. Gebreselasie ,  Steven M. Shank ,  Alain F. Loiseau ,  Robert J. Gauthier, Jr. ,  Michel J. Abou-Khalil ,  Ahmed Y. Ginawi

IPC: H01L27/06 ,  H01L23/525 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L21/823481 ,  H01L23/5256

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an eFuse and gate structure on a triple-well and methods of manufacture. The structure includes: a substrate comprising a bounded region; a gate structure formed within the bounded region; and an eFuse formed within the bounded region and electrically connected to the gate structure.

公开(公告)号：US11574867B2

公开(公告)日：2023-02-07

申请号：US17104078

申请日：2020-11-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ephrem G. Gebreselasie ,  Vibhor Jain ,  Yves T. Ngu ,  Johnatan A. Kantarovsky ,  Alain F. Loiseau

IPC: H01L23/52 ,  H01L23/525 ,  H01L21/8249 ,  H01L21/02 ,  H01L27/07 ,  H01L23/62 ,  H01L27/115 ,  H01L27/112 ,  H01L27/02

Abstract: An electrical fuse (e-fuse) includes a fuse link including a silicided semiconductor layer over a dielectric layer covering a gate conductor. The silicided semiconductor layer is non-planar and extends orthogonally over the gate conductor. A first terminal is electrically coupled to a first end of the fuse link, and a second terminal is electrically coupled to a second end of the fuse link. The fuse link may be formed in the same layer as an intrinsic and/or extrinsic base of a bipolar transistor. The gate conductor may control a current source for programming the e-fuse. The e-fuse reduces the footprint and the required programming energy compared to conventional e-fuses.

公开(公告)号：US20220165663A1

公开(公告)日：2022-05-26

申请号：US17104078

申请日：2020-11-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ephrem G. Gebreselasie ,  Vibhor Jain ,  Yves T. Ngu ,  Johnatan A. Kantarovsky ,  Alain F. Loiseau

IPC: H01L23/525 ,  H01L27/07 ,  H01L21/02 ,  H01L21/8249

Abstract: An electrical fuse (e-fuse) includes a fuse link including a silicided semiconductor layer over a dielectric layer covering a gate conductor. The silicided semiconductor layer is non-planar and extends orthogonally over the gate conductor. A first terminal is electrically coupled to a first end of the fuse link, and a second terminal is electrically coupled to a second end of the fuse link. The fuse link may be formed in the same layer as an intrinsic and/or extrinsic base of a bipolar transistor. The gate conductor may control a current source for programming the e-fuse. The e-fuse reduces the footprint and the required programming energy compared to conventional e-fuses.

公开(公告)号：US20240105595A1

公开(公告)日：2024-03-28

申请号：US17934389

申请日：2022-09-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Santosh Sharma ,  Michael J. Zierak ,  Steven J. Bentley ,  Ephrem G. Gebreselasie

IPC: H01L23/525 ,  H01L21/76 ,  H01L27/06 ,  H01L29/20

CPC classification number: H01L23/5256 ,  H01L21/7605 ,  H01L27/0605 ,  H01L29/2003

Abstract: Embodiments of the disclosure provide an electrically programmable fuse (efuse) over crystalline semiconductor material. A structure according to the disclosure includes a plurality of crystalline semiconductor layers. Each crystalline semiconductor layer includes a compound material. A metallic layer is on the plurality of crystalline semiconductor layers. The metallic layer has a lower resistivity than an uppermost layer of the plurality of crystalline semiconductor layers. A pair of gate conductors is on respective portions of the metallic layer. The metallic layer defines an electrically programmable fuse (efuse) link between the gate conductors.

公开(公告)号：US20240074167A1

公开(公告)日：2024-02-29

申请号：US17895156

申请日：2022-08-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Ephrem G. Gebreselasie ,  Rajendran Krishnasamy ,  Alain F. Loiseau

IPC: H01L27/112 ,  H01L23/525 ,  H01L29/735

CPC classification number: H01L27/11206 ,  H01L23/5256 ,  H01L29/735

Abstract: Embodiments of the disclosure provide a circuit structure including an electrically programmable fuse (efuse) and lateral bipolar transistor. A structure of the disclosure includes a lateral bipolar transistor within a semiconductor layer and over a substrate. An insulator layer is over a portion of the semiconductor layer. An efuse structure is within a polycrystalline semiconductor layer and over the insulator layer. The efuse structure is over a current path through the lateral bipolar transistor.

公开(公告)号：US20230088425A1

公开(公告)日：2023-03-23

申请号：US17483104

申请日：2021-09-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ephrem G. Gebreselasie ,  Steven M. Shank ,  Alain F. Loiseau ,  Robert J. Gauthier, JR. ,  Michel J. Abou-Khalil ,  Ahmed Y. Ginawi

IPC: H01L27/06 ,  H01L21/8234 ,  H01L23/525

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an eFuse and gate structure on a triple-well and methods of manufacture. The structure includes: a substrate comprising a bounded region; a gate structure formed within the bounded region; and an eFuse formed within the bounded region and electrically connected to the gate structure.

公开(公告)号：US11322497B1

公开(公告)日：2022-05-03

申请号：US17172539

申请日：2021-02-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yves T. Ngu ,  Ephrem G. Gebreselasie ,  Vibhor Jain ,  Johnatan A. Kantarovsky

IPC: H01L27/102 ,  H01L23/525 ,  H01L23/62

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electronic fuse (e-fuse) cells integrated with a bipolar device and methods of manufacture. The structure includes: a bipolar device comprising a collector region, a base region and an emitter region; and an e-fuse integrated with and extending from the emitter region of the bipolar device.

公开(公告)号：US20240234409A1

公开(公告)日：2024-07-11

申请号：US18152420

申请日：2023-01-10

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  Ephrem G. Gebreselasie ,  Rajendran Krishnasamy ,  Robert J. Gauthier, JR. ,  Souvick Mitra

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: The disclosure provides a structure including an n-type well over an n-type deep well and between a pair of p-type wells for electrostatic discharge (ESD) protection. The structure may include a p-type deep well over a substrate, a first n-type well over the p-type deep well, and a pair of p-type wells over the p-type deep well. The pair of p-type wells are each adjacent opposite horizontal ends of the n-type well. A pair of second n-type wells are over the p-type deep well and adjacent one of the pair of p-type wells. Each p-type well is horizontally between the first n-type well and one of the second n-type wells.