公开(公告)号：US20220208599A1

公开(公告)日：2022-06-30

申请号：US17696348

申请日：2022-03-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Uzma RANA ,  Anthony K. STAMPER ,  Steven M. SHANK ,  Brett T. CUCCI

IPC: H01L21/76 ,  H01L27/06 ,  H01L21/762 ,  H01L21/26

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.

公开(公告)号：US20220262900A1

公开(公告)日：2022-08-18

申请号：US17738179

申请日：2022-05-06

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Uzma RANA ,  Anthony K. STAMPER ,  Johnatan A. KANTAROVSKY ,  Steven M. SHANK ,  Siva P. ADUSUMILLI

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/763 ,  H01L29/10

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.

公开(公告)号：US20220115262A1

公开(公告)日：2022-04-14

申请号：US17069098

申请日：2020-10-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Uzma RANA ,  Anthony K. STAMPER ,  Steven M. SHANK ,  Brett T. CUCCI

IPC: H01L21/76 ,  H01L21/26

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.

公开(公告)号：US20220399372A1

公开(公告)日：2022-12-15

申请号：US17344391

申请日：2021-06-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. STAMPER ,  Uzma RANA ,  Siva P. ADUSUMILLI ,  Steven M. SHANK

IPC: H01L27/12 ,  H01L29/45 ,  H01L29/49 ,  H01L21/28 ,  H01L21/285 ,  H01L21/84

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.

公开(公告)号：US20220028971A1

公开(公告)日：2022-01-27

申请号：US16939213

申请日：2020-07-27

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Uzma RANA ,  Anthony K. STAMPER ,  Johnatan A. KANTAROVSKY ,  Steven M. SHANK ,  Siva P. ADUSUMILLI

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.

公开(公告)号：US20230378183A1

公开(公告)日：2023-11-23

申请号：US18231322

申请日：2023-08-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. STAMPER ,  Uzma RANA ,  Siva P. ADUSUMILLI ,  Steven M. SHANK

IPC: H01L27/12 ,  H01L29/45 ,  H01L21/84 ,  H01L21/28 ,  H01L21/285 ,  H01L29/49

CPC classification number: H01L27/1203 ,  H01L29/45 ,  H01L21/84 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/4933

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.

公开(公告)号：US20220384659A1

公开(公告)日：2022-12-01

申请号：US17330780

申请日：2021-05-26

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. STAMPER ,  Uzma RANA ,  Steven M. SHANK ,  Mark D. LEVY

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure having source/drain regions; at least one isolation structure within the source/drain regions in a substrate material; and semiconductor material on a surface of the at least one isolation structure in the source/drain regions.