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公开(公告)号:US20230402453A1
公开(公告)日:2023-12-14
申请号:US18231510
申请日:2023-08-08
IPC分类号: H01L27/082 , H01L27/06 , H01L29/737 , H01L29/06
CPC分类号: H01L27/082 , H01L27/0647 , H01L29/737 , H01L29/0646
摘要: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.
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公开(公告)号:US20230299132A1
公开(公告)日:2023-09-21
申请号:US18324637
申请日:2023-05-26
发明人: Vibhor JAIN , Anthony K. STAMPER , John J. ELLIS-MONAGHAN , Steven M. SHANK , Rajendran KRISHNASAMY
IPC分类号: H01L29/06 , H01L29/08 , H01L29/66 , H01L29/737 , H01L21/763 , H01L29/165
CPC分类号: H01L29/0642 , H01L29/0826 , H01L29/66242 , H01L29/7371 , H01L21/763 , H01L29/165
摘要: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.
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3.
公开(公告)号:US20220399372A1
公开(公告)日:2022-12-15
申请号:US17344391
申请日:2021-06-10
摘要: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.
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公开(公告)号:US20220028971A1
公开(公告)日:2022-01-27
申请号:US16939213
申请日:2020-07-27
发明人: Uzma RANA , Anthony K. STAMPER , Johnatan A. KANTAROVSKY , Steven M. SHANK , Siva P. ADUSUMILLI
IPC分类号: H01L29/06 , H01L29/78 , H01L21/762
摘要: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.
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公开(公告)号:US20210217849A1
公开(公告)日:2021-07-15
申请号:US16743589
申请日:2020-01-15
摘要: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors with back gate contact and buried high resistivity layer and methods of manufacture. The structure includes: a handle wafer comprising a single crystalline semiconductor region; an insulator layer over the single crystalline semiconductor region; a semiconductor layer over the insulator layer; a high resistivity layer in the handle wafer, separated from the insulator layer by the single crystalline semiconductor region; and a device on the semiconductor layer.
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公开(公告)号:US20240297216A1
公开(公告)日:2024-09-05
申请号:US18659282
申请日:2024-05-09
IPC分类号: H01L29/06 , H01L21/02 , H01L21/762 , H01L21/764
CPC分类号: H01L29/0649 , H01L21/02505 , H01L21/7624 , H01L21/764
摘要: The present disclosure relates to semiconductor structures and, more particularly, to a semiconductor on insulator substrate with cavity structures and methods of manufacture. The structure includes: a bulk substrate with at least one rectilinear cavity structure; an insulator material sealing the at least one rectilinear cavity structure; and a buried insulator layer on the bulk substrate and over the at least one rectilinear cavity structure.
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7.
公开(公告)号:US20230378183A1
公开(公告)日:2023-11-23
申请号:US18231322
申请日:2023-08-08
CPC分类号: H01L27/1203 , H01L29/45 , H01L21/84 , H01L21/28052 , H01L21/28518 , H01L29/4933
摘要: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.
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公开(公告)号:US20220384659A1
公开(公告)日:2022-12-01
申请号:US17330780
申请日:2021-05-26
发明人: Anthony K. STAMPER , Uzma RANA , Steven M. SHANK , Mark D. LEVY
IPC分类号: H01L29/786 , H01L29/06 , H01L29/66
摘要: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure having source/drain regions; at least one isolation structure within the source/drain regions in a substrate material; and semiconductor material on a surface of the at least one isolation structure in the source/drain regions.
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公开(公告)号:US20220122968A1
公开(公告)日:2022-04-21
申请号:US17075056
申请日:2020-10-20
IPC分类号: H01L27/082 , H01L29/06 , H01L29/737 , H01L27/06
摘要: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.
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公开(公告)号:US20220028992A1
公开(公告)日:2022-01-27
申请号:US17498241
申请日:2021-10-11
IPC分类号: H01L29/423 , H01L29/78 , H01L29/66
摘要: The present disclosure relates to semiconductor structures and, more particularly, to vertically stacked field effect transistors and methods of manufacture. The structure includes: at least one lower gate structure on a bottom of a trench formed in substrate material; insulator material partially filling trench and over the at least one lower gate structure; an epitaxial material on the insulator material and isolated from sidewalls of the trench; and at least one upper gate structure stacked vertically above the at least one lower gate structure and located on the epitaxial material.
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