公开(公告)号：US20230402453A1

公开(公告)日：2023-12-14

申请号：US18231510

申请日：2023-08-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor JAIN ,  John J. ELLIS-MONAGHAN ,  Anthony K. STAMPER ,  Steven M. SHANK ,  John J. PEKARIK

IPC: H01L27/082 ,  H01L27/06 ,  H01L29/737 ,  H01L29/06

CPC classification number: H01L27/082 ,  H01L27/0647 ,  H01L29/737 ,  H01L29/0646

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

公开(公告)号：US20230299132A1

公开(公告)日：2023-09-21

申请号：US18324637

申请日：2023-05-26

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor JAIN ,  Anthony K. STAMPER ,  John J. ELLIS-MONAGHAN ,  Steven M. SHANK ,  Rajendran KRISHNASAMY

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/737 ,  H01L21/763 ,  H01L29/165

CPC classification number: H01L29/0642 ,  H01L29/0826 ,  H01L29/66242 ,  H01L29/7371 ,  H01L21/763 ,  H01L29/165

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.

公开(公告)号：US20220399372A1

公开(公告)日：2022-12-15

申请号：US17344391

申请日：2021-06-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. STAMPER ,  Uzma RANA ,  Siva P. ADUSUMILLI ,  Steven M. SHANK

IPC: H01L27/12 ,  H01L29/45 ,  H01L29/49 ,  H01L21/28 ,  H01L21/285 ,  H01L21/84

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.

公开(公告)号：US20220028971A1

公开(公告)日：2022-01-27

申请号：US16939213

申请日：2020-07-27

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Uzma RANA ,  Anthony K. STAMPER ,  Johnatan A. KANTAROVSKY ,  Steven M. SHANK ,  Siva P. ADUSUMILLI

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.

公开(公告)号：US20210217849A1

公开(公告)日：2021-07-15

申请号：US16743589

申请日：2020-01-15

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Vibhor JAIN ,  Anthony K. STAMPER ,  Steven M. SHANK ,  John J. ELLIS-MONAGHAN ,  John J. PEKARIK

IPC: H01L29/10 ,  H01L27/12 ,  H01L29/78 ,  H01L21/74 ,  H01L21/84

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors with back gate contact and buried high resistivity layer and methods of manufacture. The structure includes: a handle wafer comprising a single crystalline semiconductor region; an insulator layer over the single crystalline semiconductor region; a semiconductor layer over the insulator layer; a high resistivity layer in the handle wafer, separated from the insulator layer by the single crystalline semiconductor region; and a device on the semiconductor layer.

公开(公告)号：US20220208599A1

公开(公告)日：2022-06-30

申请号：US17696348

申请日：2022-03-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Uzma RANA ,  Anthony K. STAMPER ,  Steven M. SHANK ,  Brett T. CUCCI

IPC: H01L21/76 ,  H01L27/06 ,  H01L21/762 ,  H01L21/26

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.

公开(公告)号：US20210384297A1

公开(公告)日：2021-12-09

申请号：US16893855

申请日：2020-06-05

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Henry L. ALDRIDGE, JR. ,  Anthony K. STAMPER ,  Jeonghyun HWANG ,  Johnatan A. KANTAROVSKY

IPC: H01L29/08 ,  H01L29/737 ,  H01L29/417 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a first semiconductor layer including a device region; a second semiconductor layer under the first semiconductor layer; a layer of conductive material between the first semiconductor layer and the second semiconductor layer; at least one contact extending to and contacting the layer of conductive material; and a device in the device region above the layer of conductive material.

公开(公告)号：US20210217850A1

公开(公告)日：2021-07-15

申请号：US16743584

申请日：2020-01-15

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Anthony K. STAMPER ,  Steven M. SHANK ,  John J. PEKARIK ,  Vibhor JAIN ,  John J. ELLIS-MONAGHAN

IPC: H01L29/16 ,  H01L21/02 ,  H01L27/12 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a wafer with crystalline silicon and trap rich polysilicon layer and methods of manufacture. The structure includes: semiconductor-on-insulator (SOI) wafer composed of a lower crystalline semiconductor layer, a polysilicon layer over the lower crystalline semiconductor layer, an upper crystalline semiconductor layer over the polysilicon layer, a buried insulator layer over the upper crystalline semiconductor layer, and a top crystalline semiconductor layer over the buried insulator layer.

公开(公告)号：US20250015128A1

公开(公告)日：2025-01-09

申请号：US18894485

申请日：2024-09-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor JAIN ,  Anthony K. STAMPER ,  John J. ELLIS-MONAGHAN ,  Steven M. SHANK ,  Rajendran KRISHNASAMY

IPC: H01L29/06 ,  H01L21/763 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.

公开(公告)号：US20240297216A1

公开(公告)日：2024-09-05

申请号：US18659282

申请日：2024-05-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anthony K. STAMPER ,  Siva P. ADUSUMILLI ,  Bruce W. PORTH ,  John J. ELLIS-MONAGHAN

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L21/764

CPC classification number: H01L29/0649 ,  H01L21/02505 ,  H01L21/7624 ,  H01L21/764

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a semiconductor on insulator substrate with cavity structures and methods of manufacture. The structure includes: a bulk substrate with at least one rectilinear cavity structure; an insulator material sealing the at least one rectilinear cavity structure; and a buried insulator layer on the bulk substrate and over the at least one rectilinear cavity structure.