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公开(公告)号:US11823948B2
公开(公告)日:2023-11-21
申请号:US17696348
申请日:2022-03-16
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Uzma Rana , Anthony K. Stamper , Steven M. Shank , Brett T. Cucci
IPC: H01L27/00 , H01L21/76 , H01L27/06 , H01L21/762
CPC classification number: H01L21/76 , H01L21/762 , H01L27/0617
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.
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公开(公告)号:US11322387B1
公开(公告)日:2022-05-03
申请号:US17069098
申请日:2020-10-13
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Uzma Rana , Anthony K. Stamper , Steven M. Shank , Brett T. Cucci
IPC: H01L27/00 , H01L21/76 , H01L21/26 , H01L27/06 , H01L21/762
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.
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公开(公告)号:US11764225B2
公开(公告)日:2023-09-19
申请号:US17344391
申请日:2021-06-10
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Anthony K. Stamper , Uzma Rana , Siva P. Adusumilli , Steven M. Shank
CPC classification number: H01L27/1203 , H01L21/28052 , H01L21/28518 , H01L21/84 , H01L29/45 , H01L29/4933
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.
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公开(公告)号:US12142686B2
公开(公告)日:2024-11-12
申请号:US17330780
申请日:2021-05-26
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Anthony K. Stamper , Uzma Rana , Steven M. Shank , Mark D. Levy
IPC: H01L29/786 , H01L29/06 , H01L29/66
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure having source/drain regions; at least one isolation structure within the source/drain regions in a substrate material; and semiconductor material on a surface of the at least one isolation structure in the source/drain regions.
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公开(公告)号:US11749717B2
公开(公告)日:2023-09-05
申请号:US17738179
申请日:2022-05-06
Applicant: GLOBALFOUNDRIES U.S. INC.
Inventor: Uzma Rana , Anthony K. Stamper , Johnatan A. Kantarovsky , Steven M. Shank , Siva P. Adusumilli
IPC: H01L29/06 , H01L21/762 , H01L29/78 , H01L29/66 , H01L21/8234 , H01L21/763 , H01L29/10
CPC classification number: H01L29/0653 , H01L21/763 , H01L21/76264 , H01L21/76283 , H01L21/823481 , H01L29/1095 , H01L29/66681 , H01L29/7816 , H01L29/7841
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.
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公开(公告)号:US11380759B2
公开(公告)日:2022-07-05
申请号:US16939213
申请日:2020-07-27
Applicant: GLOBALFOUNDRIES U.S. INC.
Inventor: Uzma Rana , Anthony K. Stamper , Johnatan A. Kantarovsky , Steven M. Shank , Siva P. Adusumilli
IPC: H01L29/06 , H01L21/762 , H01L29/78 , H01L29/66 , H01L21/763 , H01L21/8234 , H01L29/10
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.
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