Transactional Memory that Performs a Direct 32-bit Lookup Operation
    1.
    发明申请
    Transactional Memory that Performs a Direct 32-bit Lookup Operation 有权
    执行直接32位查找操作的事务内存

    公开(公告)号:US20140025918A1

    公开(公告)日:2014-01-23

    申请号:US13552605

    申请日:2012-07-18

    CPC classification number: H04L12/4625 G06F9/3004 G06F12/06 G06F15/163

    Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a base address, a starting bit position, and a mask size. In response to the lookup command, the TM pulls an input value (IV). The TM uses the starting bit position and the mask size to select a portion of the IV. A first sub-portion of the portion of the IV and the base address are summed to generate a memory address. The memory address is used to read a word containing multiple result values (RVs) from memory. One RV from the word is selected using a multiplexing circuit and a second sub-portion of the portion of the IV. If the selected RV is a final value, then lookup operation is complete and the TM sends the RV to the processor, otherwise the TM performs another lookup operation based upon the selected RV.

    Abstract translation: 事务存储器(TM)从处理器接收总线上的查找命令。 该命令包括基地址,起始位位置和掩码大小。 响应于查找命令,TM拉取输入值(IV)。 TM使用起始位位置和掩码大小来选择IV的一部分。 将IV的部分和基地址的第一子部分相加以生成存储器地址。 存储器地址用于从存储器读取包含多个结果值(RV)的单词。 使用多路复用电路和IV部分的第二子部分选择来自该单词的一个RV。 如果所选的RV是最终值,则查找操作完成,并且TM将RV发送到处理器,否则TM基于所选择的RV执行另一查找操作。

    Transactional memory that performs a direct 32-bit lookup operation
    2.
    发明授权
    Transactional memory that performs a direct 32-bit lookup operation 有权
    执行直接32位查找操作的事务内存

    公开(公告)号:US09100212B2

    公开(公告)日:2015-08-04

    申请号:US13552605

    申请日:2012-07-18

    CPC classification number: H04L12/4625 G06F9/3004 G06F12/06 G06F15/163

    Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a base address, a starting bit position, and a mask size. In response to the lookup command, the TM pulls an input value (IV). The TM uses the starting bit position and the mask size to select a portion of the IV. A first sub-portion of the portion of the IV and the base address are summed to generate a memory address. The memory address is used to read a word containing multiple result values (RVs) from memory. One RV from the word is selected using a multiplexing circuit and a second sub-portion of the portion of the IV. If the selected RV is a final value, then lookup operation is complete and the TM sends the RV to the processor, otherwise the TM performs another lookup operation based upon the selected RV.

    Abstract translation: 事务存储器(TM)从处理器接收总线上的查找命令。 该命令包括基地址,起始位位置和掩码大小。 响应于查找命令,TM拉取输入值(IV)。 TM使用起始位位置和掩码大小来选择IV的一部分。 将IV的部分和基地址的第一子部分相加以生成存储器地址。 存储器地址用于从存储器读取包含多个结果值(RV)的单词。 使用多路复用电路和IV部分的第二子部分选择来自该单词的一个RV。 如果所选的RV是最终值,则查找操作完成,并且TM将RV发送到处理器,否则TM基于所选择的RV执行另一查找操作。

    Flow control using a local event ring in an island-based network flow processor
    3.
    发明授权
    Flow control using a local event ring in an island-based network flow processor 有权
    在基于岛屿的网络流处理器中使用本地事件环的流控制

    公开(公告)号:US08929376B2

    公开(公告)日:2015-01-06

    申请号:US13400008

    申请日:2012-02-17

    CPC classification number: H04L49/9047 H04L47/13 H04L49/102 H04L49/9084

    Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh event bus extends through the islands and is configured to form a local event ring. The configurable mesh event bus is configured with configuration information received via a configurable mesh control bus. The local event ring involves event ring circuits and event ring segments. In one example, a packet is received onto a first island. If an amount of a processing resource (for example, memory buffer space) available to the first island is below a threshold, then an event packet is communicated from the first island to a second island via the local event ring. In response, the second island causes a third island to communicate via a command/push/pull data bus with the first island, thereby increasing the amount of the processing resource available to the first island for handing incoming packets.

    Abstract translation: 基于岛屿的网络流处理器(IB-NFP)集成电路包括以行组织的岛屿。 可配置的网状事件总线延伸穿过岛,并配置为形成本地事件环。 配置的mesh事件总线配置有通过可配置的网状控制总线接收的配置信息。 本地事件环包括事件环电路和事件环段。 在一个示例中,分组被接收到第一岛上。 如果第一岛可用的处理资源(例如,存储器缓冲空间)的量低于阈值,则事件分组通过本地事件环从第一岛传送到第二岛。 作为响应,第二岛使得第三岛通过命令/推/拉数据总线与第一岛进行通信,从而增加第一岛可用于处理输入分组的处理资源的量。

    Processing resource management in an island-based network flow processor
    4.
    发明授权
    Processing resource management in an island-based network flow processor 有权
    在基于岛屿的网络流处理器中处理资源管理

    公开(公告)号:US08559436B2

    公开(公告)日:2013-10-15

    申请号:US13399958

    申请日:2012-02-17

    CPC classification number: H04L12/6418

    Abstract: An island-based network flow processor (IB-NFP) integrated circuit has a high performance processor island. The processor island has a processor and a tightly coupled memory. The integrated circuit also has another memory. The other memory may be internal or external memory. The header of an incoming packet is stored in the tightly coupled memory of the processor island. The payload is stored in the other memory. In one example, if the amount of a processing resource is below a threshold then the header is moved from the first island to the other memory before the header and payload are communicated to an egress island for outputting from the integrated circuit. If, however, the amount of the processing resource is not below the threshold then the header is moved directly from the processor island to the egress island and is combined with the payload there for outputting from the integrated circuit.

    Abstract translation: 基于岛屿的网络流处理器(IB-NFP)集成电路具有高性能的处理器岛。 处理器岛具有处理器和紧耦合的存储器。 该集成电路还具有另一个存储器。 其他内存可能是内部或外部存储器。 输入分组的报头被存储在处理器岛的紧耦合存储器中。 有效载荷存储在另一个存储器中。 在一个示例中,如果处理资源的量低于阈值,则在首标和有效载荷被传送到出口岛以从集成电路输出之前,首标从第一岛移动到另一个存储器。 然而,如果处理资源的数量不低于阈值,则标题直接从处理器岛移动到出口岛,并且与有效载荷组合以从集成电路输出。

    Flow Control Using a Local Event Ring In An Island-Based Network Flow Processor
    5.
    发明申请
    Flow Control Using a Local Event Ring In An Island-Based Network Flow Processor 有权
    在基于岛屿的网络流处理器中使用本地事件环的流控制

    公开(公告)号:US20130215901A1

    公开(公告)日:2013-08-22

    申请号:US13400008

    申请日:2012-02-17

    CPC classification number: H04L49/9047 H04L47/13 H04L49/102 H04L49/9084

    Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh event bus extends through the islands and is configured to form a local event ring. The configurable mesh event bus is configured with configuration information received via a configurable mesh control bus. The local event ring involves event ring circuits and event ring segments. In one example, a packet is received onto a first island. If an amount of a processing resource (for example, memory buffer space) available to the first island is below a threshold, then an event packet is communicated from the first island to a second island via the local event ring. In response, the second island causes a third island to communicate via a command/push/pull data bus with the first island, thereby increasing the amount of the processing resource available to the first island for handing incoming packets.

    Abstract translation: 基于岛屿的网络流处理器(IB-NFP)集成电路包括以行组织的岛屿。 可配置的网状事件总线延伸穿过岛,并配置为形成本地事件环。 配置的mesh事件总线配置有通过可配置的网状控制总线接收的配置信息。 本地事件环包括事件环电路和事件环段。 在一个示例中,分组被接收到第一岛上。 如果第一岛可用的处理资源(例如,存储器缓冲空间)的量低于阈值,则事件分组通过本地事件环从第一岛传送到第二岛。 作为响应,第二岛使得第三岛通过命令/推/拉数据总线与第一岛进行通信,从而增加第一岛可用于处理输入分组的处理资源的量。

    Processing Resource Management In An Island-Based Network Flow Processor
    6.
    发明申请
    Processing Resource Management In An Island-Based Network Flow Processor 有权
    在基于岛屿的网络流处理器中处理资源管理

    公开(公告)号:US20130215893A1

    公开(公告)日:2013-08-22

    申请号:US13399958

    申请日:2012-02-17

    CPC classification number: H04L12/6418

    Abstract: An island-based network flow processor (IB-NFP) integrated circuit has a high performance processor island. The processor island has a processor and a tightly coupled memory. The integrated circuit also has another memory. The other memory may be internal or external memory. The header of an incoming packet is stored in the tightly coupled memory of the processor island. The payload is stored in the other memory. In one example, if the amount of a processing resource is below a threshold then the header is moved from the first island to the other memory before the header and payload are communicated to an egress island for outputting from the integrated circuit. If, however, the amount of the processing resource is not below the threshold then the header is moved directly from the processor island to the egress island and is combined with the payload there for outputting from the integrated circuit.

    Abstract translation: 基于岛屿的网络流处理器(IB-NFP)集成电路具有高性能的处理器岛。 处理器岛具有处理器和紧耦合的存储器。 该集成电路还具有另一个存储器。 其他内存可能是内部或外部存储器。 输入分组的报头被存储在处理器岛的紧耦合存储器中。 有效载荷存储在另一个存储器中。 在一个示例中,如果处理资源的量低于阈值,则在首标和有效载荷被传送到出口岛以从集成电路输出之前,首标从第一岛移动到另一个存储器。 然而,如果处理资源的数量不低于阈值,则标题直接从处理器岛移动到出口岛,并且与有效载荷组合以从集成电路输出。

    Packet switch with multiple addressable components
    8.
    发明授权
    Packet switch with multiple addressable components 有权
    分组交换机具有多个可寻址组件

    公开(公告)号:US07356628B2

    公开(公告)日:2008-04-08

    申请号:US11129600

    申请日:2005-05-13

    CPC classification number: G06F13/4022

    Abstract: An integrated circuit on which are implemented a number of devices that conform to the Rapidio network architecture. Included in the integrated circuit are two addressed RapidIO devices and switching devices which provide 24 switching ports. The devices have a packet receiving side and a packet transmitting side; the packet receiving side of each of the devices is connected by 128-bit wide paths termed poles its own packet transmitting side and each of the other transmitting sides. Features of the integrated circuit include centralized multicasting and configuration control for all of the devices on the integrated circuit, provisions for having more than one address in a RapidIO device, techniques for defining the address space routed by a routing table, techniques for managing congestion, and advanced buffer management techniques.

    Abstract translation: 实现了符合Rapidio网络架构的多个设备的集成电路。 集成电路中包含两个提供24个交换端口的RapidIO设备和交换设备。 这些设备具有分组接收侧和分组发送侧; 每个设备的分组接收侧由其自己的分组发送侧和每个其他发送侧的被称为极点的128位宽路径连接。 集成电路的特征包括集成电路上的所有设备的集中多播和配置控制,在RapidIO设备中具有多于一个地址的规定,用于定义由路由表路由的地址空间的技术,用于管理拥塞的技术, 和先进的缓冲管理技术。

    Apparatus and method for measuring conditions in fluidized beds
    9.
    发明授权
    Apparatus and method for measuring conditions in fluidized beds 失效
    用于测量流化床条件的装置和方法

    公开(公告)号:US6008662A

    公开(公告)日:1999-12-28

    申请号:US741917

    申请日:1996-10-31

    CPC classification number: B01J8/1809 C08F10/00 G01N27/60

    Abstract: Conditions in a fluidized bed are measured with a probe and a circuit. The bed can be a polymerization reactor's reaction chamber, and the conditions can result in "sheeting" which is the build up of polymer on the chamber walls. The probe protrudes into the bed and detects a current which generally is a function of at least the impact and charge of particulates in the bed. The current detected by the probe is related to the conditions in the bed. The circuit measures the detected current. The probe has an inner probe piece of metallic material within an insulator of polymeric material. A portion of the insulator protrudes a first distance into the bed, and a portion of the inner probe piece protrudes a second distance into the bed. The first distance is less than or equal to the second distance. The insulator typically does not extend as far into the bed as the inner probe piece.

    Abstract translation: 用探针和电路测量流化床中的条件。 床可以是聚合反应器的反应室,并且条件可导致聚合物在室壁上积聚的“片材”。 探针突出到床中并检测通常至少是床中的颗粒的冲击和电荷的作用的电流。 探头检测到的电流与床上的状况有关。 电路测量检测到的电流。 探针在聚合物材料的绝缘体内具有金属材料的内部探针片。 绝缘体的一部分突出到床中的第一距离,并且内探测件的一部分突出到床的第二距离。 第一距离小于或等于第二距离。 绝缘体通常不像内部探针片一样延伸到床内。

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