公开(公告)号：US20140025918A1

公开(公告)日：2014-01-23

申请号：US13552605

申请日：2012-07-18

Applicant: Gavin J. Stark ,  Ron L. Swartzentruber

Inventor： Gavin J. Stark ,  Ron L. Swartzentruber

IPC: G06F12/10

CPC classification number: H04L12/4625 ,  G06F9/3004 ,  G06F12/06 ,  G06F15/163

Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a base address, a starting bit position, and a mask size. In response to the lookup command, the TM pulls an input value (IV). The TM uses the starting bit position and the mask size to select a portion of the IV. A first sub-portion of the portion of the IV and the base address are summed to generate a memory address. The memory address is used to read a word containing multiple result values (RVs) from memory. One RV from the word is selected using a multiplexing circuit and a second sub-portion of the portion of the IV. If the selected RV is a final value, then lookup operation is complete and the TM sends the RV to the processor, otherwise the TM performs another lookup operation based upon the selected RV.

Abstract translation: 事务存储器（TM）从处理器接收总线上的查找命令。 该命令包括基地址，起始位位置和掩码大小。 响应于查找命令，TM拉取输入值（IV）。 TM使用起始位位置和掩码大小来选择IV的一部分。 将IV的部分和基地址的第一子部分相加以生成存储器地址。 存储器地址用于从存储器读取包含多个结果值（RV）的单词。 使用多路复用电路和IV部分的第二子部分选择来自该单词的一个RV。 如果所选的RV是最终值，则查找操作完成，并且TM将RV发送到处理器，否则TM基于所选择的RV执行另一查找操作。

公开(公告)号：US09100212B2

公开(公告)日：2015-08-04

申请号：US13552605

申请日：2012-07-18

Applicant: Gavin J. Stark ,  Ron L. Swartzentruber

Inventor： Gavin J. Stark ,  Ron L. Swartzentruber

IPC: G06F12/00 ,  H04L12/46 ,  G06F12/06 ,  G06F9/30 ,  G06F15/163

CPC classification number: H04L12/4625 ,  G06F9/3004 ,  G06F12/06 ,  G06F15/163

Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a base address, a starting bit position, and a mask size. In response to the lookup command, the TM pulls an input value (IV). The TM uses the starting bit position and the mask size to select a portion of the IV. A first sub-portion of the portion of the IV and the base address are summed to generate a memory address. The memory address is used to read a word containing multiple result values (RVs) from memory. One RV from the word is selected using a multiplexing circuit and a second sub-portion of the portion of the IV. If the selected RV is a final value, then lookup operation is complete and the TM sends the RV to the processor, otherwise the TM performs another lookup operation based upon the selected RV.

Abstract translation: 事务存储器（TM）从处理器接收总线上的查找命令。 该命令包括基地址，起始位位置和掩码大小。 响应于查找命令，TM拉取输入值（IV）。 TM使用起始位位置和掩码大小来选择IV的一部分。 将IV的部分和基地址的第一子部分相加以生成存储器地址。 存储器地址用于从存储器读取包含多个结果值（RV）的单词。 使用多路复用电路和IV部分的第二子部分选择来自该单词的一个RV。 如果所选的RV是最终值，则查找操作完成，并且TM将RV发送到处理器，否则TM基于所选择的RV执行另一查找操作。

公开(公告)号：US08929376B2

公开(公告)日：2015-01-06

申请号：US13400008

申请日：2012-02-17

Applicant: Gavin J. Stark ,  Steven W. Zagorianakos ,  Ron L. Swartzentruber ,  Richard P. Bouley

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos ,  Ron L. Swartzentruber ,  Richard P. Bouley

IPC: H04L12/54 ,  G06F15/80

CPC classification number: H04L49/9047 ,  H04L47/13 ,  H04L49/102 ,  H04L49/9084

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh event bus extends through the islands and is configured to form a local event ring. The configurable mesh event bus is configured with configuration information received via a configurable mesh control bus. The local event ring involves event ring circuits and event ring segments. In one example, a packet is received onto a first island. If an amount of a processing resource (for example, memory buffer space) available to the first island is below a threshold, then an event packet is communicated from the first island to a second island via the local event ring. In response, the second island causes a third island to communicate via a command/push/pull data bus with the first island, thereby increasing the amount of the processing resource available to the first island for handing incoming packets.

Abstract translation: 基于岛屿的网络流处理器（IB-NFP）集成电路包括以行组织的岛屿。 可配置的网状事件总线延伸穿过岛，并配置为形成本地事件环。 配置的mesh事件总线配置有通过可配置的网状控制总线接收的配置信息。 本地事件环包括事件环电路和事件环段。 在一个示例中，分组被接收到第一岛上。 如果第一岛可用的处理资源（例如，存储器缓冲空间）的量低于阈值，则事件分组通过本地事件环从第一岛传送到第二岛。 作为响应，第二岛使得第三岛通过命令/推/拉数据总线与第一岛进行通信，从而增加第一岛可用于处理输入分组的处理资源的量。

公开(公告)号：US08559436B2

公开(公告)日：2013-10-15

申请号：US13399958

申请日：2012-02-17

Applicant: Gavin J. Stark ,  Steven W. Zagorianakos ,  Ron L. Swartzentruber

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos ,  Ron L. Swartzentruber

IPC: H04L12/28 ,  H04L12/54 ,  G06F15/173

CPC classification number: H04L12/6418

Abstract: An island-based network flow processor (IB-NFP) integrated circuit has a high performance processor island. The processor island has a processor and a tightly coupled memory. The integrated circuit also has another memory. The other memory may be internal or external memory. The header of an incoming packet is stored in the tightly coupled memory of the processor island. The payload is stored in the other memory. In one example, if the amount of a processing resource is below a threshold then the header is moved from the first island to the other memory before the header and payload are communicated to an egress island for outputting from the integrated circuit. If, however, the amount of the processing resource is not below the threshold then the header is moved directly from the processor island to the egress island and is combined with the payload there for outputting from the integrated circuit.

Abstract translation: 基于岛屿的网络流处理器（IB-NFP）集成电路具有高性能的处理器岛。 处理器岛具有处理器和紧耦合的存储器。 该集成电路还具有另一个存储器。 其他内存可能是内部或外部存储器。 输入分组的报头被存储在处理器岛的紧耦合存储器中。 有效载荷存储在另一个存储器中。 在一个示例中，如果处理资源的量低于阈值，则在首标和有效载荷被传送到出口岛以从集成电路输出之前，首标从第一岛移动到另一个存储器。 然而，如果处理资源的数量不低于阈值，则标题直接从处理器岛移动到出口岛，并且与有效载荷组合以从集成电路输出。

公开(公告)号：US20130215901A1

公开(公告)日：2013-08-22

申请号：US13400008

申请日：2012-02-17

Applicant: Gavin J. Stark ,  Steven W. Zagorianakos ,  Ron L. Swartzentruber ,  Richard P. Bouley

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos ,  Ron L. Swartzentruber ,  Richard P. Bouley

IPC: H04L12/56

CPC classification number: H04L49/9047 ,  H04L47/13 ,  H04L49/102 ,  H04L49/9084

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh event bus extends through the islands and is configured to form a local event ring. The configurable mesh event bus is configured with configuration information received via a configurable mesh control bus. The local event ring involves event ring circuits and event ring segments. In one example, a packet is received onto a first island. If an amount of a processing resource (for example, memory buffer space) available to the first island is below a threshold, then an event packet is communicated from the first island to a second island via the local event ring. In response, the second island causes a third island to communicate via a command/push/pull data bus with the first island, thereby increasing the amount of the processing resource available to the first island for handing incoming packets.

Abstract translation: 基于岛屿的网络流处理器（IB-NFP）集成电路包括以行组织的岛屿。 可配置的网状事件总线延伸穿过岛，并配置为形成本地事件环。 配置的mesh事件总线配置有通过可配置的网状控制总线接收的配置信息。 本地事件环包括事件环电路和事件环段。 在一个示例中，分组被接收到第一岛上。 如果第一岛可用的处理资源（例如，存储器缓冲空间）的量低于阈值，则事件分组通过本地事件环从第一岛传送到第二岛。 作为响应，第二岛使得第三岛通过命令/推/拉数据总线与第一岛进行通信，从而增加第一岛可用于处理输入分组的处理资源的量。

公开(公告)号：US20130215893A1

公开(公告)日：2013-08-22

申请号：US13399958

申请日：2012-02-17

Applicant: Gavin J. Stark ,  Steven W. Zagorianakos ,  Ron L. Swartzentruber

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos ,  Ron L. Swartzentruber

IPC: H04L12/56

CPC classification number: H04L12/6418

Abstract: An island-based network flow processor (IB-NFP) integrated circuit has a high performance processor island. The processor island has a processor and a tightly coupled memory. The integrated circuit also has another memory. The other memory may be internal or external memory. The header of an incoming packet is stored in the tightly coupled memory of the processor island. The payload is stored in the other memory. In one example, if the amount of a processing resource is below a threshold then the header is moved from the first island to the other memory before the header and payload are communicated to an egress island for outputting from the integrated circuit. If, however, the amount of the processing resource is not below the threshold then the header is moved directly from the processor island to the egress island and is combined with the payload there for outputting from the integrated circuit.

Abstract translation: 基于岛屿的网络流处理器（IB-NFP）集成电路具有高性能的处理器岛。 处理器岛具有处理器和紧耦合的存储器。 该集成电路还具有另一个存储器。 其他内存可能是内部或外部存储器。 输入分组的报头被存储在处理器岛的紧耦合存储器中。 有效载荷存储在另一个存储器中。 在一个示例中，如果处理资源的量低于阈值，则在首标和有效载荷被传送到出口岛以从集成电路输出之前，首标从第一岛移动到另一个存储器。 然而，如果处理资源的数量不低于阈值，则标题直接从处理器岛移动到出口岛，并且与有效载荷组合以从集成电路输出。

公开(公告)号：US09098264B2

公开(公告)日：2015-08-04

申请号：US13552627

申请日：2012-07-18

Applicant: Gavin J. Stark ,  Hetal Sanket Borad

Inventor： Gavin J. Stark ,  Hetal Sanket Borad

IPC: G06F12/00 ,  G06F9/30 ,  G06F12/06 ,  G06F15/163

CPC classification number: G06F9/3001 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/06 ,  G06F15/163

Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. Only final result values are stored in memory. The command includes a base address, a starting bit position, and mask size. In response to the lookup command, the TM pulls an input value (IV). A selecting circuit within the TM uses the starting bit position and mask size to select a portion of the IV. The portion of the IV and the base address are used to generate a memory address. The memory address is used to read a word containing multiple result values (RVs) from memory. One RV from the word is selected using a multiplexing circuit and a result location value (RLV) generated from the portion of the IV. A word selector circuit and arithmetic circuits are used to generate the memory address and RLV. The TM sends the selected RV to the processor.

Abstract translation: 事务存储器（TM）从处理器接收总线上的查找命令。 只有最终的结果值存储在内存中。 该命令包括基地址，起始位位置和掩码大小。 响应于查找命令，TM拉取输入值（IV）。 TM内的选择电路使用起始位位置和掩码大小来选择IV的一部分。 IV和基地址的部分用于生成内存地址。 存储器地址用于从存储器读取包含多个结果值（RV）的单词。 使用多路复用电路和从IV部分产生的结果位置值（RLV）来选择来自该单词的一个RV。 字选择器电路和运算电路用于产生存储器地址和RLV。 TM将所选择的RV发送到处理器。

公开(公告)号：US08902902B2

公开(公告)日：2014-12-02

申请号：US13552555

申请日：2012-07-18

Applicant: Gavin J. Stark ,  Bruce Alexander Wilford

Inventor： Gavin J. Stark ,  Bruce Alexander Wilford

IPC: G06F7/02 ,  H03K17/00 ,  G06F13/40 ,  H04L12/745 ,  H04L12/741

CPC classification number: H03K17/00 ,  G06F9/467 ,  G06F13/40 ,  H04L45/745 ,  H04L45/748

Abstract: A hardware trie structure includes a tree of internal node circuits and leaf node circuits. Each internal node is configured by a corresponding multi-bit node control value (NCV). Each leaf node can output a corresponding result value (RV). An input value (IV) supplied onto input leads of the trie causes signals to propagate through the trie such that one of the leaf nodes outputs one of the RVs onto output leads of the trie. In a transactional memory, a memory stores a set of NCVs and RVs. In response to a lookup command, the NCVs and RVs are read out of memory and are used to configure the trie. The IV of the lookup is supplied to the input leads, and the trie looks up an RV. A non-final RV initiates another lookup in a recursive fashion, whereas a final RV is returned as the result of the lookup command.

Abstract translation: 硬件特里结构包括一棵内部节点电路和叶节点电路。 每个内部节点由相应的多位节点控制值（NCV）配置。 每个叶节点可以输出相应的结果值（RV）。 提供给特里的输入引线的输入值（IV）使得信号通过三通传播，使得一个叶节点将其中一个RV输出到该线索的输出引线。 在事务存储器中，存储器存储一组NCV和RV。 响应于查找命令，NCV和RV从存储器中读出并用于配置特里。 查询的IV被提供给输入引线，并且特技查找RV。 非最终RV以递归方式发起另一次查找，而作为查找命令的结果返回最终RV。

公开(公告)号：US08775686B2

公开(公告)日：2014-07-08

申请号：US13598533

申请日：2012-08-29

Applicant: Gavin J. Stark

Inventor： Gavin J. Stark

IPC: G06F3/00 ,  G06F13/00 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06

CPC classification number: G06F9/467 ,  G06F12/00 ,  G06F13/1615 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/4234 ,  H04L45/745 ,  Y02D10/14 ,  Y02D10/151

Abstract: A transactional memory (TM) receives an Atomic Metering Command (AMC) across a bus from a processor. The command includes a memory address and a meter pair indicator value. In response to the AMC, the TM pulls an input value (IV). The TM uses the memory address to read a word including multiple credit values from a memory unit. Circuitry within the TM selects a pair of credit values, subtracts the IV from each of the pair of credit values thereby generating a pair of decremented credit values, compares the pair of decremented credit values with a threshold value, respectively, thereby generating a pair of indicator values, performs a lookup based upon the pair of indicator values and the meter pair indicator value, and outputs a selector value and a result value that represents a meter color. The selector value determines the credit values written back to the memory unit.

Abstract translation: 事务存储器（TM）从处理器接收总线上的原子计量命令（AMC）。 该命令包括存储器地址和仪表对指示器值。 对于AMC，TM提取输入值（IV）。 TM使用存储器地址从存储器单元读取包括多个信用值的单词。 TM内的电路选择一对信用值，从该对信用值中的每一个中减去IV，从而生成一对递减的信用值，将一对递减的信用值与阈值进行比较，从而产生一对 指示符值，根据指示符值对和仪表对指示符值执行查找，并输出选择器值和表示仪表颜色的结果值。 选择器值确定写入存储单元的信用值。

公开(公告)号：US20130219100A1

公开(公告)日：2013-08-22

申请号：US13399433

申请日：2012-02-17

Applicant: Gavin J. Stark

Inventor： Gavin J. Stark

IPC: G06F13/36

CPC classification number: G06F13/4022 ,  G06F13/00 ,  G06F13/28 ,  G06F17/5072 ,  G06F17/5077 ,  H04L12/54 ,  H04L12/56 ,  H04L51/00

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes rectangular islands disposed in rows. In one example, the configurable mesh data bus is configurable to form a command/push/pull data bus over which multiple transactions can occur simultaneously on different parts of the integrated circuit. The rectangular islands of one row are oriented in staggered relation with respect to the rectangular islands of the next row. The left and right edges of islands in a row align with left and right edges of islands two rows down in the row structure. The data bus involves multiple meshes. In each mesh, the island has a centrally located crossbar switch and six radiating half links, and half links down to functional circuitry of the island. The staggered orientation of the islands, and the structure of the half links, allows half links of adjacent islands to align with one another.

Abstract translation: 基于岛屿的网络流处理器（IB-NFP）集成电路包括以行排列的矩形岛。 在一个示例中，可配置的网格数据总线可配置成形成命令/推/拉数据总线，多个事务可以同时发生在集成电路的不同部分上。 一行的矩形岛相对于下一行的矩形岛定向成交错关系。 一行中的岛的左边缘和右边缘与行结构中两行向下的岛的左边缘和右边缘对齐。 数据总线涉及多个网格。 在每个网格中，岛具有位于中心的交叉开关和六个辐射半连接，并且一半连接到岛的功能电路。 岛屿的交错取向和半连接的结构允许相邻岛屿的一半链接彼此对齐。