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1.发明授权
公开(公告)号：US5175832A
公开(公告)日：1992-12-29
申请号：US355922
申请日：1989-05-23
申请人： George Keryvel , Jean-Louis Thomas , Claude Timsit
发明人： George Keryvel , Jean-Louis Thomas , Claude Timsit
CPC分类号： G06F5/06 , G06F13/1673
摘要： A memory including several modules with each module receiving at the input requests coming from a processor and furnishing at the output the responses to these requests. The requests are transmitted to the input of each module via an input shift register. The responses coming from a module are transmitted to the input of a processor via an output shift register. The number of stages of the input shift register is different for each of the modules and the total number of stages for the input and output shift registers associated with one of the modules is constant and independent of the module in question.
摘要翻译： 包括几个模块的存储器，每个模块在输入来自处理器的请求中接收并在输出端提供对这些请求的响应。 这些请求通过输入移位寄存器发送到每个模块的输入。 来自模块的响应经由输出移位寄存器传送到处理器的输入端。 输入移位寄存器的级数对于每个模块是不同的，并且与一个模块相关联的输入和输出移位寄存器的总级数是恒定的并且与所讨论的模块无关。
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2.发明授权System having constant number of total input and output shift registers stages for each processor to access different memory modules 失效具有总输入和输出移位寄存器的持续数量的系统每个处理器访问不同存储器模块的阶段
公开(公告)号：US5170483A
公开(公告)日：1992-12-08
申请号：US391141
申请日：1989-08-08
CPC分类号： G06F15/8092 , G06F13/1657 , G06F15/8007
摘要： A central unit for a data-processing system having a high degree of parallelism. This central unit includes a number of basic processors sending requests to a number of modules in receiving responses from those modules. To simplify the interconnection between the modules and the processors when their number increases, the invention is characterized wherein the requests sent from each processor are transmitted to the input of each of said modules via an input shift register, wherein the response coming from each of the said modules are transmitted to the input of each processor via an output shift register, wherein for any provided processor, the number of stages of said input shift register making it possible to access the modules is different for each of the modules and wherein for any processor, the total number of stages belonging to the input and output shift registers associated with one of the said modules is constant and independent of the module and processor in question.
摘要翻译： 用于具有高度并行性的数据处理系统的中央单元。 该中央单元包括许多基本处理器，向多个模块发送请求以接收来自这些模块的响应。 为了简化模块和处理器之间的互连，当其数量增加时，本发明的特征在于，其中从每个处理器发送的请求经由输入移位寄存器被发送到每个所述模块的输入，其中来自 所述模块经由输出移位寄存器传输到每个处理器的输入端，其中对于任何提供的处理器，使得可以访问模块的所述输入移位寄存器的级数为每个模块不同，并且对于任何处理器 属于与所述模块中的一个模块相关联的输入和输出移位寄存器的阶段总数是恒定的并且与所讨论的模块和处理器无关。
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公开(公告)号：US4849929A
公开(公告)日：1989-07-18
申请号：US253698
申请日：1988-10-05
申请人： Claude Timsit
发明人： Claude Timsit
CPC分类号： G06F11/1076 , G06F11/1008 , G06F3/0601 , G11B20/1833 , G06F2003/0692
摘要： A method of recording numerical information in a plurality of disk units, in which the bits of each word of numerical information are transmitted simultaneously, each bit being allocated to a unit associated with the weight of that bit in that word, and a memory system for implementing the method, including a main controller (2) provided with a selector enabling the distribution and synchronization of the information signals.
摘要翻译： 一种在多个盘单元中记录数字信息的方法，其中数字信息的每个字的位同时发送，每个位分配给与该字中该位的权重相关联的单元，以及存储系统， 实现该方法，包括设置有能够进行信息信号分配和同步的选择器的主控制器（2）。
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公开(公告)号：US4817035A
公开(公告)日：1989-03-28
申请号：US712174
申请日：1985-03-15
申请人： Claude Timsit
发明人： Claude Timsit
CPC分类号： G06F11/1076 , G06F11/1008 , G06F3/0601 , G11B20/1833 , G06F2003/0692
摘要： A method of recording numerical information in a plurality of disk units, in which the bits of each word of numerical information are transmitted simultaneously, each bit being allocated to a unit associated with the weight of that bit in that word, and a memory system for implementing the method, including a main controller (2) provided with a selector enabling the distribution and synchronization of the information signals.
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公开(公告)号：US4057795A
公开(公告)日：1977-11-08
申请号：US624124
申请日：1975-10-20
申请人： Claude Timsit
发明人： Claude Timsit
IPC分类号： H03M1/00 , H03K13/175
CPC分类号： H03M1/365
摘要： This encoder comprises a series of resistors for determining the reference voltages, and comparators having at least one pair of outputs A and B. First inputs of said comparators are connected respectively to said resistors and second inputs of said comparators are connected to the voltage to be encoded through an impedance adaptor stage. The outputs A and B of the pairs of outputs of each comparator are respectively connected to the outputs B and A of the following comparator and constitute first and second output groups. The first and second groups are connected respectively to the inputs of a comparator constituting a bit of smallest weight of the encoder and the outputs A and B of the other pairs of outputs are connected in a similar manner to comparators constituting bits of greatest weight.
摘要翻译： 该编码器包括用于确定参考电压的一系列电阻器，以及具有至少一对输出A和B的比较器。所述比较器的第一输入端分别连接到所述电阻器，所述比较器的第二输入端连接到电压 通过阻抗适配器级编码。 每个比较器的输出对的输出A和B分别连接到以下比较器的输出B和A，并构成第一和第二输出组。 第一组和第二组分别连接到构成编码器的最小权重位的比较器的输入端，而另一对输出的输出A和B以与构成最大权重的比较器相似的方式连接。
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公开(公告)号：US4144566A
公开(公告)日：1979-03-13
申请号：US823854
申请日：1977-08-11
申请人： Claude Timsit
发明人： Claude Timsit
CPC分类号： G06F15/8007
摘要： A parallel processor having a large number of elementary processors connected in parallel to an address bus and a control bus. Each elementary processor contains a memory and control and processing circuits to perform calculations on bits addressed in the memory and bits coming either from this memory or from a peripheral unit. Each elementary processor further contains a small capacity fast memory and the control and processing circuit contains a single storage flip-flop able to perform calculations in series on the bits extracted from the memories and/or coming from the peripheral unit. All the fast memories are parallel connected.
摘要翻译： 具有与地址总线和控制总线并联连接的大量基本处理器的并行处理器。 每个基本处理器都包含一个存储器和控制和处理电路，用于对存储器中寻址的位进行计算，以及从该存储器或来自外围单元的位。 每个基本处理器还包含一个小容量的快速存储器，并且控制和处理电路包含能够对从存储器提取的位和/或来自外围单元的位进行串行计算的单个存储触发器。 所有的快速记忆都是并联的。
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