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公开(公告)号：US20140253177A1
公开(公告)日：2014-09-11
申请号：US14285660
申请日：2014-05-23
Applicant: Google Inc.
Inventor： Lynn Bos , Arnold Feldman , Shahriar Rabii
IPC: G11C27/02
CPC classification number: G11C27/028 , G11C27/02 , G11C27/024
Abstract: A circuit with a sampling network may include a pair of capacitors, where each of the capacitors has a first node and a second node; a first pair of switches communicatively coupling corresponding differential input voltage signals to the first node of each of the capacitors; and a second pair of switches communicatively coupling the second node of each of the capacitors to a common mode voltage source. Corresponding differential output voltage signals at the second node of each of the capacitors may be communicatively coupled using a differential switch. The second pair of switches may be coupled in parallel with the differential switch. A clock signal of the differential switch may be de-asserted prior to de-asserting corresponding clock signals for each of the second pair of switches.
Abstract translation: 具有采样网络的电路可以包括一对电容器，其中每个电容器具有第一节点和第二节点; 第一对开关，其将相应的差分输入电压信号通信耦合到每个电容器的第一节点; 以及第二对开关，其将每个电容器的第二节点通信地耦合到共模电压源。 每个电容器的第二节点处的对应差分输出电压信号可以使用差分开关通信耦合。 第二对开关可以与差动开关并联。 差分开关的时钟信号可以在对于第二对开关中的每一个的对应时钟信号解除置位之前被解除断言。
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公开(公告)号：US09946899B1
公开(公告)日：2018-04-17
申请号：US15294525
申请日：2016-10-14
Applicant: Google Inc.
Inventor： William Wesson , Scott Johnson , Lynn Bos
Abstract: Provided are systems, methods, and apparatus for protecting an integrated circuit against invasive attacks and various forms of tampering. A defensive mechanism is an active physical security shield that includes an array of traces at a high metal of the integrated circuit, covering a high percentage of the surface area of that layer, and a collection of digital logic components that drive signals across the traces. The driving of the signals across the traces is done in an active manner such that a short, open, or stuck-at fault on any of the traces is detected within a very short period of time. The active security system is connected to or in communication with an alert response mechanism, such that a fault detected by the security system results in a signal being sent to the alert response mechanism.
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公开(公告)号：US10331410B2
公开(公告)日：2019-06-25
申请号：US15347593
申请日：2016-11-09
Applicant: Google Inc.
Inventor： William Wesson , Scott Johnson , Karthika Periyathambi , Lynn Bos
Abstract: A true random number generator (TRNG) uses an analog circuit with a ring oscillator configured to collapse from an unstable oscillation state to a stable oscillation state at a random collapse time and counter counting a counter value representing the random collapse time. Various techniques are used to harden the TRNG including a truncator generating a true random number based on a truncation of the reference count value and a dedicated voltage regulator supplying power to the analog core including the ring oscillator. Techniques also include various solutions for drawing a constant current such as using a Gray code counter and adding noise current during and/or after the collapse event with a dummy inverter chain. Bit churning, bit obfuscation entropy enhancers and various post processing techniques may be employed to further harden the TRNG. An attack detection module may raise alerts when the TRNG is being attacked.
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公开(公告)号：US09171642B2
公开(公告)日：2015-10-27
申请号：US14285660
申请日：2014-05-23
Applicant: Google Inc.
Inventor： Lynn Bos , Arnold Feldman , Shahriar Rabii
CPC classification number: G11C27/028 , G11C27/02 , G11C27/024
Abstract: A circuit with a sampling network may include a pair of capacitors, where each of the capacitors has a first node and a second node; a first pair of switches communicatively coupling corresponding differential input voltage signals to the first node of each of the capacitors; and a second pair of switches communicatively coupling the second node of each of the capacitors to a common mode voltage source. Corresponding differential output voltage signals at the second node of each of the capacitors may be communicatively coupled using a differential switch. The second pair of switches may be coupled in parallel with the differential switch. A clock signal of the differential switch may be de-asserted prior to de-asserting corresponding clock signals for each of the second pair of switches.
Abstract translation: 具有采样网络的电路可以包括一对电容器，其中每个电容器具有第一节点和第二节点; 第一对开关，其将相应的差分输入电压信号通信耦合到每个电容器的第一节点; 以及第二对开关，其将每个电容器的第二节点通信地耦合到共模电压源。 每个电容器的第二节点处的对应差分输出电压信号可以使用差分开关通信耦合。 第二对开关可以与差动开关并联。 差分开关的时钟信号可以在对于第二对开关中的每一个的对应时钟信号解除置位之前被解除断言。
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