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    PARTIAL CACHE COHERENCE
    2.
    发明申请
    PARTIAL CACHE COHERENCE 审中-公开

    公开(公告)号：US20180322058A1

    公开(公告)日：2018-11-08

    申请号：US15589164

    申请日：2017-05-08

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Jean Tourrilhes ,  Michael Schlansker

    IPC: G06F12/0831 ,  G06F12/0815

    CPC classification number: G06F12/0835 ,  G06F12/0813 ,  G06F12/0815 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/154 ,  G06F2212/621

    Abstract: Examples disclosed herein relate to partial cache coherence. In some examples disclosed herein, a node connected to a memory fabric may include local cache connected to a local processor and a memory coherency proxy to. The memory coherency proxy may configure a portion of a fabric memory on the memory fabric as a proxy backing memory and expose the proxy backing memory to other nodes in the memory fabric as a fictitious local memory on the node, and may implement partial coherency for memory requests directed to the fictitious local memory. The fictitious local memory may have a memory address region different from a memory address region of a native local memory on the node.

    Partial cache coherence
    4.
    发明授权
    Partial cache coherence 有权

    公开(公告)号：US10423530B2

    公开(公告)日：2019-09-24

    申请号：US15589164

    申请日：2017-05-08

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Jean Tourrilhes ,  Michael Schlansker

    IPC: G06F12/0831 ,  G06F12/0815 ,  G06F12/0813

    Abstract: Examples disclosed herein relate to partial cache coherence. In some examples disclosed herein, a node connected to a memory fabric may include local cache connected to a local processor and a memory coherency proxy to. The memory coherency proxy may configure a portion of a fabric memory on the memory fabric as a proxy backing memory and expose the proxy backing memory to other nodes in the memory fabric as a fictitious local memory on the node, and may implement partial coherency for memory requests directed to the fictitious local memory. The fictitious local memory may have a memory address region different from a memory address region of a native local memory on the node.

    Path-synchronous performance monitoring of interconnection networks based on source code attribution
    6.
    发明授权
    Path-synchronous performance monitoring of interconnection networks based on source code attribution 有权

    公开(公告)号：US10887213B2

    公开(公告)日：2021-01-05

    申请号：US15705950

    申请日：2017-09-15

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Milind M Chabbi ,  Michael Schlansker ,  Adarsh Yoga

    IPC: H04L12/26 ,  H04L29/08 ,  G06F11/30 ,  G06F11/34

    Abstract: Examples disclosed herein relate to path-synchronous performance monitoring of an interconnection network based on source code attribution. A processing node in the interconnection network has a profiler module to select a network transaction to be monitored, determine a source code attribution associated with the network transaction to be monitored, and issue a network command to execute the network transaction to be monitored. A logger module creates, in a buffer, a node temporal log associated with the network transaction and the network command. A drainer module periodically captures the node temporal log. The processing node has a network interface controller to receive the network command and mark a packet generated for the network command to be temporally tracked and attributed back to the source code attribution at each hop of the interconnection network traversed by the marked packet.

    PATH-SYNCHRONOUS PERFORMANCE MONITORING OF INTERCONNECTION NETWORKS BASED ON SOURCE CODE ATTRIBUTION
    8.
    发明申请
    PATH-SYNCHRONOUS PERFORMANCE MONITORING OF INTERCONNECTION NETWORKS BASED ON SOURCE CODE ATTRIBUTION 审中-公开

    公开(公告)号：US20190089616A1

    公开(公告)日：2019-03-21

    申请号：US15705950

    申请日：2017-09-15

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Milind M. Chabbi ,  Michael Schlansker ,  Adarsh Yoga

    IPC: H04L12/26 ,  G06F11/30 ,  G06F11/34 ,  H04L29/08

    Abstract: Examples disclosed herein relate to path-synchronous performance monitoring of an interconnection network based on source code attribution. A processing node in the interconnection network has a profiler module to select a network transaction to be monitored, determine a source code attribution associated with the network transaction to be monitored, and issue a network command to execute the network transaction to be monitored. A logger module creates, in a buffer, a node temporal log associated with the network transaction and the network command. A drainer module periodically captures the node temporal log. The processing node has a network interface controller to receive the network command and mark a packet generated for the network command to be temporally tracked and attributed back to the source code attribution at each hop of the interconnection network traversed by the marked packet.

    A SWITCHING FABRIC INCLUDING A VIRTUAL SWITCH
    9.
    发明申请
    A SWITCHING FABRIC INCLUDING A VIRTUAL SWITCH 审中-公开
    一种包括虚拟开关的开关织物

    公开(公告)号：US20170070473A1

    公开(公告)日：2017-03-09

    申请号：US15119789

    申请日：2014-03-14

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Michael Schlansker ,  Jean Tourrilhes ,  Jose Renato G. Santos ,  Paul Allen Bottorff

    IPC: H04L29/12 ,  H04L12/709 ,  H04L12/64

    CPC classification number: H04L61/103 ,  H04L12/6418 ,  H04L45/245

    Abstract: A method may include determining whether a host destination address of a packet received at a particular switch of a switching fabric is associated with a virtual switch address. In response to a determination that the host destination address is associated with the virtual switch address, the method may also include encapsulating the packet with the virtual switch address as a destination fabric address, where the virtual switch address is associated with a virtual switch including a first physical switch and a second physical switch. The method may further include selecting one of the first physical switch and the second physical switch as a routing path. The method may further include routing the packet to the selected physical switch based on the virtual switch address and transmitting the packet from the selected physical switch to a client switch.

    Abstract translation: 方法可以包括确定在交换结构的特定交换机处接收到的分组的主机目的地址是否与虚拟交换机地址相关联。 响应于确定主机目的地地址与虚拟交换机地址相关联，该方法还可以包括将具有虚拟交换机地址的分组封装为目的结构地址，其中虚拟交换机地址与虚拟交换机地址相关联，虚拟交换机包括 第一个物理开关和第二个物理开关。 该方法还可以包括选择第一物理交换机和第二物理交换机之一作为路由路径。 该方法还可以包括基于虚拟交换机地址将分组路由到所选择的物理交换机，并将分组从所选择的物理交换机发送到客户端交换机。

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