公开(公告)号：US20160247565A1

公开(公告)日：2016-08-25

申请号：US15031813

申请日：2013-10-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Frederick Perner ,  Kwangmyoung Rho ,  Jeong Hwan Kim ,  Sangmin Hwang ,  Jinwon Park ,  Jae Yun Yi ,  Jae Yeon Lee ,  Sung Won Chung

IPC: G11C13/00 ,  H01L27/24

CPC classification number: G11C13/0028 ,  G11C8/10 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04

Abstract: In one example, a three dimensional resistive memory architecture includes adjacent memory tiles with each tile including a multilevel resistive crossbar. array and at least one decoder. The multilevel crossbar array includes layers of row crossbars, layers of column crossbars, and layers of resistive memory elements interposed between cross points of the row crossbars and the column crossbars, in which at least one layer of crossbars extends from a first tile through an adjacent tile and is used to address resistive memory elements in the adjacent tile. The at least one decoder underlies the multilevel resistive crossbar array and includes an address matrix comprising digital lines and analog lines, in which the digital lines select which crossbars are connected to the analog lines.

Abstract translation: 在一个示例中，三维电阻存储器架构包括相邻的存储器块，每个瓦片包括多电平电阻交叉开关。 阵列和至少一个解码器。 所述多级交叉开关阵列包括插入所述行十字条和所述列交叉条的交叉点之间的行交叉条，列交叉条层和电阻性存储器元件层，其中至少一层交叉条从第一瓦片延伸穿过相邻的 并且用于寻址相邻瓦片中的电阻性存储器元件。 所述至少一个解码器位于所述多电平电阻交叉开关阵列之下，并且包括包括数字线和模拟线的地址矩阵，其中所述数字线选择哪些交叉连接到所述模拟线。

公开(公告)号：US09792980B2

公开(公告)日：2017-10-17

申请号：US15031813

申请日：2013-10-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Frederick Perner ,  Kwangmyoung Rho ,  Jeong Hwan Kim ,  Sangmin Hwang ,  Jinwon Park ,  Jae Yun Yi ,  Jae Yeon Lee ,  Sung Won Chung

IPC: G11C8/10 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0028 ,  G11C8/10 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04

Abstract: In one example, a three dimensional resistive memory architecture includes adjacent memory tiles with each tile including a multilevel resistive crossbar array and at least one decoder. The multilevel crossbar array includes layers of row crossbars, layers of column crossbars, and layers of resistive memory elements interposed between cross points of the row crossbars and the column crossbars, in which at least one layer of crossbars extends from a first tile through an adjacent tile and is used to address resistive memory elements in the adjacent tile. The at least one decoder underlies the multilevel resistive crossbar array and includes an address matrix comprising digital lines and analog lines, in which the digital lines select which crossbars are connected to the analog lines.