中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.018 seconds)

    RESISTIVE CROSSPOINT MEMORY ARRAY SENSING
    1.
    发明申请
    RESISTIVE CROSSPOINT MEMORY ARRAY SENSING 有权
    电阻式记忆阵列感测

    公开(公告)号：US20160267970A1

    公开(公告)日：2016-09-15

    申请号：US15031106

    申请日：2013-10-29

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Frederick Perner ,  Yoocharn Jeon

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/15 ,  G11C2213/72 ,  G11C2213/73

    Abstract: A method includes applying a voltage bump across a combined memory device comprising a volatile selector switch and a nonvolatile switch, in which the voltage bump changes a state of the volatile selector switch from a high resistance to a low resistance but does not change a state of the nonvolatile switch. A read voltage that is lower than the voltage bump across the combined memory device to read a state of the nonvolatile switch.

    Abstract translation: 一种方法包括在包括易失性选择器开关和非易失性开关的组合存储器件中施加电压突起，其中电压凸起将易失性选择器开关的状态从高电阻改变为低电阻，但不改变 非易失性开关。 读取电压低于组合存储器件上的电压突起，以读取非易失性开关的状态。

    THREE DIMENSIONAL RESISTIVE MEMORY ARCHITECTURES
    3.
    发明申请
    THREE DIMENSIONAL RESISTIVE MEMORY ARCHITECTURES 有权
    三维电容式存储器架构

    公开(公告)号：US20160247565A1

    公开(公告)日：2016-08-25

    申请号：US15031813

    申请日：2013-10-31

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Frederick Perner ,  Kwangmyoung Rho ,  Jeong Hwan Kim ,  Sangmin Hwang ,  Jinwon Park ,  Jae Yun Yi ,  Jae Yeon Lee ,  Sung Won Chung

    IPC: G11C13/00 ,  H01L27/24

    CPC classification number: G11C13/0028 ,  G11C8/10 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04

    Abstract: In one example, a three dimensional resistive memory architecture includes adjacent memory tiles with each tile including a multilevel resistive crossbar. array and at least one decoder. The multilevel crossbar array includes layers of row crossbars, layers of column crossbars, and layers of resistive memory elements interposed between cross points of the row crossbars and the column crossbars, in which at least one layer of crossbars extends from a first tile through an adjacent tile and is used to address resistive memory elements in the adjacent tile. The at least one decoder underlies the multilevel resistive crossbar array and includes an address matrix comprising digital lines and analog lines, in which the digital lines select which crossbars are connected to the analog lines.

    Abstract translation: 在一个示例中，三维电阻存储器架构包括相邻的存储器块，每个瓦片包括多电平电阻交叉开关。 阵列和至少一个解码器。 所述多级交叉开关阵列包括插入所述行十字条和所述列交叉条的交叉点之间的行交叉条，列交叉条层和电阻性存储器元件层，其中至少一层交叉条从第一瓦片延伸穿过相邻的 并且用于寻址相邻瓦片中的电阻性存储器元件。 所述至少一个解码器位于所述多电平电阻交叉开关阵列之下，并且包括包括数字线和模拟线的地址矩阵，其中所述数字线选择哪些交叉连接到所述模拟线。

    Memory controllers
    4.
    发明授权
    Memory controllers 有权

    公开(公告)号：US09911490B2

    公开(公告)日：2018-03-06

    申请号：US15314687

    申请日：2014-05-30

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Ning Ge ,  Jianhua Yang ,  Frederick Perner ,  Janice H. Nickel

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2013/0045 ,  G11C2213/77

    Abstract: A memory controller includes a voltage control module that operates to isolate a target memristor of a memory crossbar array. The voltage control module applies a column voltage to a column line coupled to the target memristor, applies a first row voltage to all row lines not coupled to the target memristor and a second row voltage to a row line coupled to the target memristor, and senses a current through the target memristor to determine a state of the target memristor. The memory crossbar array includes a plurality of column lines, a plurality of row lines, a plurality of memristors, and a plurality of shorting switches. Each memristor is coupled between a unique combination of one column line and one row line. Each shorting switch has a high impedance resistor and a low impedance transistor, and each shorting switch is coupled to an end of a unique row line.

    GEOMETRY DEPENDENT VOLTAGE BIASES FOR ASYMMETRIC RESISTIVE MEMORIES
    6.
    发明申请
    GEOMETRY DEPENDENT VOLTAGE BIASES FOR ASYMMETRIC RESISTIVE MEMORIES 有权
    用于不对称电阻记忆的几何相关电压偏置

    公开(公告)号：US20160247563A1

    公开(公告)日：2016-08-25

    申请号：US15030092

    申请日：2013-10-28

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Frederick Perner

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C5/025 ,  G11C5/147 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0069

    Abstract: In one example, a system includes a multi-plane memory array with shared crossbars and memory elements accessed through the shared crossbars and support circuitry. The support circuitry includes a bias multiplexer to determine an orientation of a target memory element in the multi-plane memory array and output voltage biases with a polarity based on the orientation of the target memory element. Methods for generating and applying geometry dependent voltage biases are also provided.

    Abstract translation: 在一个示例中，系统包括具有通过共享交叉开关和支持电路访问的共享交叉开关和存储器元件的多平面存储器阵列。 支持电路包括偏置多路复用器，用于基于目标存储元件的取向来确定多平面存储器阵列中的目标存储器元件的取向和具有极性的输出电压偏压。 还提供了生成和应用几何相关电压偏压的方法。

    Resistive crosspoint memory array sensing
    7.
    发明授权
    Resistive crosspoint memory array sensing 有权
    电阻式交叉点存储器阵列感测

    公开(公告)号：US09558820B2

    公开(公告)日：2017-01-31

    申请号：US15031106

    申请日：2013-10-29

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Frederick Perner ,  Yoocharn Jeon

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/15 ,  G11C2213/72 ,  G11C2213/73

    Abstract: A method includes applying a voltage bump across a combined memory device comprising a volatile selector switch and a nonvolatile switch, in which the voltage bump changes a state of the volatile selector switch from a high resistance to a low resistance but does not change a state of the nonvolatile switch. A read voltage that is lower than the voltage bump across the combined memory device to read a state of the nonvolatile switch.

    Abstract translation: 一种方法包括在包括易失性选择器开关和非易失性开关的组合存储器件中施加电压突起，其中电压凸起将易失性选择器开关的状态从高电阻改变为低电阻，但不改变 非易失性开关。 读取电压低于组合存储器件上的电压突起，以读取非易失性开关的状态。

    MEMORY CONTROLLERS
    8.
    发明申请
    MEMORY CONTROLLERS 有权

    公开(公告)号：US20170200494A1

    公开(公告)日：2017-07-13

    申请号：US15314687

    申请日：2014-05-30

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Ning Ge ,  Jianhua Yang ,  Frederick Perner ,  Janice H. Nickel

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2013/0045 ,  G11C2213/77

    Abstract: A memory controller includes a voltage control module that operates to isolate a target memristor of a memory crossbar array. The voltage control module applies a column voltage to a column line coupled to the target memristor, applies a first row voltage to all row lines not coupled to the target memristor and a second row voltage to a row line coupled to the target memristor, and senses a current through the target memristor to determine a state of the target memristor. The memory crossbar array includes a plurality of column lines, a plurality of row lines, a plurality of memristors, and a plurality of shorting switches. Each memristor is coupled between a unique combination of one column line and one row line. Each shorting switch has a high impedance resistor and a low impedance transistor, and each shorting switch is coupled to an end of a unique row line.

Patent Agency Ranking