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    Integrated circuit with flash memory
    1.
    发明授权
    Integrated circuit with flash memory 有权

    公开(公告)号：US06574142B2

    公开(公告)日：2003-06-03

    申请号：US09891428

    申请日：2001-06-26

    申请人： Hans-Joachim Gelke ,  Axel Hertwig ,  Stefan Koch

    发明人： Hans-Joachim Gelke ,  Axel Hertwig ,  Stefan Koch

    IPC分类号： G11C1604

    CPC分类号： G11C16/102

    摘要： This invention relates to the structure and design of microprocessor ICs, in particular to the embedding or integration of a non-volatile flash memory (7) into an IC. To integrate such a flash memory into an IC raises some problems which are solved by providing a dedicated flash bus (3) which operationally links the flash memory (7) with one or more microprocessors (1, 2) on the IC. Preferably, the flash bus (3) controls the flash-memory-specific commands and has a width greater than, in particular a multiple of, the width of the microprocessor (1, 2) and/or the flash memory (7) to compensate for the relatively slow access time of the flash memory. It is especially advantageous to structure the system as a master/slave bus system for operating the flash memory (7) and to link the flash bus via bridges (4, 5, 6) to the microprocessor/s (1, 2,) and through a shell (8) to the flash memory (7). For operating such a system, a flash bus arbiter (9) may be necessary or advantageous.

    Inter-processor communication system for communication between processors
    2.
    发明授权
    Inter-processor communication system for communication between processors 有权
    处理器间通信系统，用于处理器之间的通信

    公开(公告)号：US07313641B2

    公开(公告)日：2007-12-25

    申请号：US09947104

    申请日：2001-09-05

    申请人： Stefan Koch ,  Hans-Joachim Gelke ,  Axel Hertwig

    发明人： Stefan Koch ,  Hans-Joachim Gelke ,  Axel Hertwig

    IPC分类号： G06F13/38 ,  G06F13/28

    CPC分类号： G06F13/4004 ,  G06F13/28 ,  G06F15/167

    摘要： A system (15) comprising at least two integrated processors (P1 and P2). These two processors (P1 and P2) are operably connected via a communication channel (17) for exchanging information. One processor (P1) has a processor bus (10), a shareable unit (13), and a DMA unit (11) with an external DMA channel (12). The DMA unit (11) and the sharable unit (13) are connected to the processor bus (10). The other processor (P2) has an access unit (21) which is a connectable to the external DMA channel (12) of the DMA unit (11). Due to this arrangement, a communication channel (17) can be established from the access unit (21) which is connectable to the external DMA channel (12), the DMA unit (11), and the processor bus (10).

    摘要翻译： 一种包括至少两个集成处理器（P 1和P 2）的系统（15）。 这两个处理器（P 1和P 2）通过用于交换信息的通信信道（17）可操作地连接。 一个处理器（P 1）具有处理器总线（10），共享单元（13）和具有外部DMA通道（12）的DMA单元（11）。 DMA单元（11）和可共享单元（13）连接到处理器总线（10）。 另一个处理器（P 2）具有可连接到DMA单元（11）的外部DMA通道（12）的访问单元（21）。 由于这种布置，可以从可连接到外部DMA通道（12），DMA单元（11）和处理器总线（10）的访问单元（21）建立通信信道（17）。

    Method of operating a storage system and storage system
    3.
    发明授权
    Method of operating a storage system and storage system 有权
    操作存储系统和存储系统的方法

    公开(公告)号：US06594731B1

    公开(公告)日：2003-07-15

    申请号：US09640728

    申请日：2000-08-17

    申请人： Axel Hertwig ,  Harald Bauer ,  Urs Fawer ,  Paul Lippens

    发明人： Axel Hertwig ,  Harald Bauer ,  Urs Fawer ,  Paul Lippens

    IPC分类号： G06F1208

    CPC分类号： G06F12/0862 ,  Y02D10/13

    摘要： A method of operating a storage system comprising a main memory and a cache memory structured in address-related lines, in which cache memory can be loaded with data from the main memory and be read out by a processor as required. During the processor's access to data of a certain address in the cache memory, at which address certain data from the main memory which has a corresponding address is stored, a test is made to determine whether sequential data s stored at the next address in the cache memory; and this sequential data, if unavailable, can be loaded from the main memory in the cache memory via a prefetch, the latter only taking place when the processor accesses a predefined line section lying in a line.

    摘要翻译： 一种操作存储系统的方法，该存储系统包括主要存储器和结构在地址相关行中的高速缓存存储器，其中高速缓冲存储器可以从主存储器加载数据，并且根据需要由处理器读出。 在处理器访问高速缓冲存储器中某个地址的数据时，存储有来自主存储器的具有相应地址的某些数据，进行测试以确定存储在高速缓存中的下一个地址的顺序数据 记忆; 并且如果不可用，则该顺序数据可以经由预取从高速缓冲存储器中的主存储器加载，后者仅在处理器访问位于一行中的预定义线段时发生。

    Processor memory system
    4.
    发明授权
    Processor memory system 有权
    处理器内存系统

    公开(公告)号：US06708253B2

    公开(公告)日：2004-03-16

    申请号：US09929131

    申请日：2001-08-14

    申请人： Axel Hertwig ,  Harald Bauer ,  Urs Fawer

    发明人： Axel Hertwig ,  Harald Bauer ,  Urs Fawer

    IPC分类号： C06F1200

    CPC分类号： G06F12/0802 ,  G06F12/08 ,  G06F2212/251 ,  G06F2212/253

    摘要： A processor memory system which includes: a processor component provided with a processor and at least a first integrated RAM memory, at least one second, external memory which is coupled to the processor component via an interface, a programmable memory management component which is integrated in the processor component and checks, in the case of a data address requested by the processor, whether this data address is stored in the first RAM memory which serves as a fast memory and in which data from the external memory has been loaded in advance, wherein the memory management component indicates the RAM memory address at which the data associated with the memory address is stored if the data is present in the RAM memory, the data then being read from the RAM memory, and wherein, if the data address is not present in the RAM memory, the memory management component outputs an interrupt instruction to the processor which subsequently initiates the loading of the searched data address from the external memory into the RAM memory.

    摘要翻译： 一种处理器存储器系统，其包括：处理器部件，其具有处理器和至少第一集成RAM存储器，至少一个第二外部存储器，其经由接口耦合到所述处理器部件，所述可编程存储器管理部件集成在 处理器组件并且在处理器请求的数据地址的情况下，检查该数据地址是否存储在用作快速存储器的第一RAM存储器中，并且其中来自外部存储器的数据已预先加载，其中 如果RAM存储器中存在数据，存储器管理组件指示存储与存储器地址相关联的数据的RAM存储器地址，然后从RAM存储器读取数据，并且如果数据地址不存在 RAM存储器，存储器管理组件向处理器输出中断指令，随后从该存储器启动搜索到的数据地址的加载 外部存储器进入RAM存储器。

    Memory sharing arrangement for an integrated multiprocessor system
    6.
    发明授权
    Memory sharing arrangement for an integrated multiprocessor system 有权
    集成多处理器系统的内存共享安排

    公开(公告)号：US07761644B1

    公开(公告)日：2010-07-20

    申请号：US09640729

    申请日：2000-08-17

    申请人： Axel Hertwig ,  Harald Bauer ,  Urs Fawer ,  Paul Lippens

    发明人： Axel Hertwig ,  Harald Bauer ,  Urs Fawer ,  Paul Lippens

    IPC分类号： G06F1/00

    CPC分类号： G06F12/0806

    摘要： A multiprocessor system, more particularly for terminal devices of mobile radiotelephony, in which system are arranged on a common chip: at least two processors, at least one rewritable memory which can be accessed by the two processors, at least one cache memory via which the first processor has access to the memory, at least one bridge via which the second processor has access to the memory.

    摘要翻译： 一种多处理器系统，更具体地涉及用于移动无线电话的终端设备，其中系统被布置在公共芯片上：至少两个处理器，至少一个可由两个处理器访问的可重写存储器，至少一个缓存存储器， 第一处理器可以访问存储器，至少一个桥接器，第二处理器经由该桥接器访问存储器。

    Multiprocessor array
    8.
    发明授权
    Multiprocessor array 有权
    多处理器阵列

    公开(公告)号：US07096177B2

    公开(公告)日：2006-08-22

    申请号：US09965451

    申请日：2001-09-27

    申请人： Axel Hertwig ,  Rainer Mehling ,  Stephan Koch

    发明人： Axel Hertwig ,  Rainer Mehling ,  Stephan Koch

    IPC分类号： G06F13/12

    CPC分类号： G06F13/385 ,  G06F13/4059 ,  G06F15/16

    摘要： A multiprocessor array with a first shadow register unit (3) which operates within a first clock domain, at least one second shadow register unit (11) which operates within a second clock domain, and a peripheral unit (17) which operates within a peripheral clock domain. Within all clock domains there are provided register units (3, 11, 20) which have a construction that is functionally identical.

    摘要翻译： 一种具有在第一时钟域内操作的第一影子寄存器单元（3）的多处理器阵列，在第二时钟域内操作的至少一个第二影子寄存器单元（11）以及在外围设备中操作的外围单元（17） 时钟域。 在所有时钟域内，都提供了具有功能相同结构的寄存器单元（3,11,20）。