公开(公告)号：US06594731B1

公开(公告)日：2003-07-15

申请号：US09640728

申请日：2000-08-17

申请人： Axel Hertwig ,  Harald Bauer ,  Urs Fawer ,  Paul Lippens

发明人： Axel Hertwig ,  Harald Bauer ,  Urs Fawer ,  Paul Lippens

IPC分类号： G06F1208

CPC分类号： G06F12/0862 ,  Y02D10/13

摘要： A method of operating a storage system comprising a main memory and a cache memory structured in address-related lines, in which cache memory can be loaded with data from the main memory and be read out by a processor as required. During the processor's access to data of a certain address in the cache memory, at which address certain data from the main memory which has a corresponding address is stored, a test is made to determine whether sequential data s stored at the next address in the cache memory; and this sequential data, if unavailable, can be loaded from the main memory in the cache memory via a prefetch, the latter only taking place when the processor accesses a predefined line section lying in a line.

摘要翻译： 一种操作存储系统的方法，该存储系统包括主要存储器和结构在地址相关行中的高速缓存存储器，其中高速缓冲存储器可以从主存储器加载数据，并且根据需要由处理器读出。 在处理器访问高速缓冲存储器中某个地址的数据时，存储有来自主存储器的具有相应地址的某些数据，进行测试以确定存储在高速缓存中的下一个地址的顺序数据 记忆; 并且如果不可用，则该顺序数据可以经由预取从高速缓冲存储器中的主存储器加载，后者仅在处理器访问位于一行中的预定义线段时发生。

公开(公告)号：US07761644B1

公开(公告)日：2010-07-20

申请号：US09640729

申请日：2000-08-17

申请人： Axel Hertwig ,  Harald Bauer ,  Urs Fawer ,  Paul Lippens

发明人： Axel Hertwig ,  Harald Bauer ,  Urs Fawer ,  Paul Lippens

IPC分类号： G06F1/00

CPC分类号： G06F12/0806

摘要： A multiprocessor system, more particularly for terminal devices of mobile radiotelephony, in which system are arranged on a common chip: at least two processors, at least one rewritable memory which can be accessed by the two processors, at least one cache memory via which the first processor has access to the memory, at least one bridge via which the second processor has access to the memory.

摘要翻译： 一种多处理器系统，更具体地涉及用于移动无线电话的终端设备，其中系统被布置在公共芯片上：至少两个处理器，至少一个可由两个处理器访问的可重写存储器，至少一个缓存存储器， 第一处理器可以访问存储器，至少一个桥接器，第二处理器经由该桥接器访问存储器。

公开(公告)号：US20110091677A1

公开(公告)日：2011-04-21

申请号：US12898170

申请日：2010-10-05

申请人： Stefan Egli ,  Urs Fawer

发明人： Stefan Egli ,  Urs Fawer

IPC分类号： B42D15/10 ,  G09F3/02 ,  B32B3/02

CPC分类号： B42D25/36 ,  B42D13/00 ,  B42D25/00 ,  B42D25/24 ,  B42D25/475 ,  Y10T428/15

摘要： The data sheet comprises a plate (2) which is or can be personalized on at least one side. The plate (2) can be bound into the ID with a strip-shaped flexible connecting element (3). By means of a connection (5), the connecting element (3) is firmly connected to one edge (4) of the plate (2). The strip-shaped connecting element (3) has at least one weakened material portion (6) which makes it more difficult to detach the plate (2) from the connecting element (3) without damage. The weakened material portion (6) is, for example, an incision or a score in the connecting element (3). The invention increases the security against forgery of IDs which have such a data sheet (1).

摘要翻译： 数据表包括在至少一个侧面上或可以被个性化的板（2）。 板（2）可以用带状柔性连接元件（3）绑定到ID中。 通过连接（5），连接元件（3）牢固地连接到板（2）的一个边缘（4）。 带状连接元件（3）具有至少一个弱化材料部分（6），这使得更难以将板（2）从连接元件（3）上分离而不损坏。 弱化材料部分（6）例如是连接元件（3）中的切口或刻痕。 本发明增加了具有这种数据表（1）的ID伪造的安全性。

公开(公告)号：US06708253B2

公开(公告)日：2004-03-16

申请号：US09929131

申请日：2001-08-14

申请人： Axel Hertwig ,  Harald Bauer ,  Urs Fawer

发明人： Axel Hertwig ,  Harald Bauer ,  Urs Fawer

IPC分类号： C06F1200

CPC分类号： G06F12/0802 ,  G06F12/08 ,  G06F2212/251 ,  G06F2212/253

摘要： A processor memory system which includes: a processor component provided with a processor and at least a first integrated RAM memory, at least one second, external memory which is coupled to the processor component via an interface, a programmable memory management component which is integrated in the processor component and checks, in the case of a data address requested by the processor, whether this data address is stored in the first RAM memory which serves as a fast memory and in which data from the external memory has been loaded in advance, wherein the memory management component indicates the RAM memory address at which the data associated with the memory address is stored if the data is present in the RAM memory, the data then being read from the RAM memory, and wherein, if the data address is not present in the RAM memory, the memory management component outputs an interrupt instruction to the processor which subsequently initiates the loading of the searched data address from the external memory into the RAM memory.

摘要翻译： 一种处理器存储器系统，其包括：处理器部件，其具有处理器和至少第一集成RAM存储器，至少一个第二外部存储器，其经由接口耦合到所述处理器部件，所述可编程存储器管理部件集成在 处理器组件并且在处理器请求的数据地址的情况下，检查该数据地址是否存储在用作快速存储器的第一RAM存储器中，并且其中来自外部存储器的数据已预先加载，其中 如果RAM存储器中存在数据，存储器管理组件指示存储与存储器地址相关联的数据的RAM存储器地址，然后从RAM存储器读取数据，并且如果数据地址不存在 RAM存储器，存储器管理组件向处理器输出中断指令，随后从该存储器启动搜索到的数据地址的加载 外部存储器进入RAM存储器。