公开(公告)号：US6140188A

公开(公告)日：2000-10-31

申请号：US83251

申请日：1998-05-20

Applicant: Harlan Sur ,  Subhas Bothra

Inventor： Harlan Sur ,  Subhas Bothra

IPC: H01L27/06 ,  H01L27/11 ,  H01L21/336

CPC classification number: H01L27/0676 ,  H01L27/11

Abstract: A small-area, high-resistance load device is fabricated in the same area used for the shallow trench isolation region. In an example embodiment, the load device comprises a series resistor coupled to a poly-silicon diode. In one example application, the load device acts as a pull-up device replacing standard PMOS pull-up loads used in connection with static memory cells, thereby increasing the cell density of a static memory array.

Abstract translation: 在用于浅沟槽隔离区域的相同区域中制造小面积，高电阻负载装置。 在示例性实施例中，负载装置包括耦合到多晶硅二极管的串联电阻器。 在一个示例应用中，负载设备用作上拉设备，替代与静态存储器单元相关联使用的标准PMOS上拉负载，从而增加静态存储器阵列的单元密度。

公开(公告)号：US6133111A

公开(公告)日：2000-10-17

申请号：US164167

申请日：1998-09-30

Applicant: Harlan Sur ,  Subhas Bothra

Inventor： Harlan Sur ,  Subhas Bothra

IPC: G03F9/00 ,  H01L23/544 ,  H01L21/76

CPC classification number: G03F9/708 ,  G03F9/70 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002

Abstract: A photo alignment structure integral with a substrate enables the alignment apparatus to receive a reflected light signature of the surface topography of the alignment structure. As the circuit is constructed, the alignment target may be built in tandem with the process. The alignment structure is constructed so that its surface will retain sufficient topography to enable the alignment apparatus to properly align.

Abstract translation: 与基板一体的光取向结构使得对准装置能够接收对准结构的表面形貌的反射光标记。 当构建电路时，可以与该过程一起构建对准目标。 对准结构被构造成使得其表面将保持足够的形貌以使对准装置能够正确对准。

公开(公告)号：US5877562A

公开(公告)日：1999-03-02

申请号：US925040

申请日：1997-09-08

Applicant: Harlan Sur ,  Subhas Bothra

Inventor： Harlan Sur ,  Subhas Bothra

IPC: G03F9/00 ,  H01L23/544 ,  H01L23/58

CPC classification number: G03F9/708 ,  G03F9/70 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002

Abstract: A photo alignment structure integral with a substrate enables the alignment apparatus to receive a reflected light signature of the surface topography of the alignment structure. As the circuit is constructed, the alignment target may be built in tandem with the process. The alignment structure is constructed so that its surface will retain sufficient topography to enable the alignment apparatus to properly align.

Abstract translation: 与基板一体的光取向结构使得对准装置能够接收对准结构的表面形貌的反射光标记。 当构建电路时，可以与该过程一起构建对准目标。 对准结构被构造成使得其表面将保持足够的形貌以使对准装置能够正确对准。

公开(公告)号：US20110163831A1

公开(公告)日：2011-07-07

申请号：US13047699

申请日：2011-03-14

Applicant: Carol Barrett ,  Tom McKay ,  Subhas Bothra

Inventor： Carol Barrett ,  Tom McKay ,  Subhas Bothra

IPC: H01F5/00

CPC classification number: H01L23/5227 ,  H01F2017/0046 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

Abstract translation: 公开了一种电感器电路。 电感器电路包括第一硅芯片电感器和第二硅芯片电感器，每个具有多个匝数。 第二硅电感器的多圈的一部分形成在第一硅内感应器的匝之间。 第一和第二硅内电感器被配置为使得流过第一硅芯片电感器和第二硅芯片电感器的差分电流在相应的电感圈中以相同的方向流动。

公开(公告)号：US07614024B2

公开(公告)日：2009-11-03

申请号：US11244514

申请日：2005-10-06

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F2217/12 ,  Y02P90/265

Abstract: Embodiments of the present invention provide a system and method with which to implement metal fill during design using tools such as a place and route tools or layout tools. Unlike prior known solutions where metal fill was performed after design and layout, performing metal fill during layout with a uniform pattern of conductive traces sized and spaced according to the design rules of the device to be fabricated resulting in more planning and design. Dividing the conductive traces into active and inactive segments during the design and layout identifies potentially negative impacts on critical or sensitive device elements within the device during design and layout. Previously, metal fill was implemented after design and layout and often resulted in negative impacts not previously accounted for during IC design. Embodiments of the present invention reduce degradation, seen in other devices where metal fill is incorporated after design and layout. Additionally, because the physical characteristics of inactive metal fill segments are considered during design and layout of the ICs.

Abstract translation: 本发明的实施例提供了一种系统和方法，用于在设计期间使用诸如位置和路线工具或布局工具的工具来实现金属填充。 与在设计和布局之后执行金属填充的现有已知解决方案不同，在布局期间，根据要制造的器件的设计规则，均匀地形成导电迹线图案并进行间隔，从而实现更多的规划和设计，进行金属填充。 在设计和布局期间，将导电迹线划分为有源和无源段可以在设计和布局期间识别器件内的关键或敏感器件元件的潜在负面影响。 以前，设计和布局后实施了金属填充，并且经常导致IC设计中以前未考虑的负面影响。 本发明的实施例减少了在设计和布局之后掺入金属填充物的其他装置中的劣化。 另外，因为在IC的设计和布局期间考虑了非活性金属填充段的物理特性。

公开(公告)号：US20060273874A1

公开(公告)日：2006-12-07

申请号：US11504073

申请日：2006-08-15

Applicant: Carol Barrett ,  Tom McKay ,  Subhas Bothra

Inventor： Carol Barrett ,  Tom McKay ,  Subhas Bothra

IPC: H01F5/00

CPC classification number: H01L23/5227 ,  H01F2017/0046 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

公开(公告)号：US07095307B1

公开(公告)日：2006-08-22

申请号：US10623084

申请日：2003-07-17

Applicant: Carol Barrett ,  Tom McKay ,  Subhas Bothra

Inventor： Carol Barrett ,  Tom McKay ,  Subhas Bothra

IPC: H01F5/00

CPC classification number: H01L23/5227 ,  H01F2017/0046 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

公开(公告)号：US06492716B1

公开(公告)日：2002-12-10

申请号：US09846335

申请日：2001-04-30

Applicant: Subhas Bothra ,  Thomas G. McKay ,  Ravi Jhota

Inventor： Subhas Bothra ,  Thomas G. McKay ,  Ravi Jhota

IPC: H01L2302

CPC classification number: H01L23/564 ,  H01L23/552 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a seal ring which includes a plurality of cuts separating the seal ring into seal ring portions which are disposed adjacent to different circuits in the integrated circuit die. The cuts reduce the noise coupling among the different circuits through the seal ring. To further isolate the sensitive RF/analog circuits from the noise generated by the digital circuit, the seal ring may be electrically (for dc noise) isolated from the substrate. This is accomplished, for instance, by inserting a polysilicon layer and gate oxide between the seal ring and the substrate. In addition, an n-well/p-well capacitor may be formed in series with the gate oxide, for instance, by implanting an n-well below the polysilicon layer in a p-type substrate. In this way, the seal ring provides substantially reduced noise coupling among the circuits but still maintains an effective wall around the periphery of the die to protect the circuits against moisture and ionic contamination penetration.

Abstract translation: 本发明的实施例提供了一种密封环，其包括将密封环分隔成密封环部分的多个切口，所述密封环部分邻近集成电路管芯中的不同电路设置。 切割可以通过密封环减少不同电路之间的噪声耦合。 为了进一步将敏感的RF /模拟电路与数字电路产生的噪声隔离开，密封环可能是与基板隔离的电气（用于直流噪声）。 这通过例如在密封环和衬底之间插入多晶硅层和栅极氧化物来实现。 此外，n阱/ p阱电容器可以与栅极氧化物串联形成，例如通过在p型衬底中注入多晶硅层下面的n阱。 以这种方式，密封环在电路之间提供显着降低的噪声耦合，但仍然保持围绕芯片周边的有效壁，以保护电路免受潮湿和离子污染的渗透。

公开(公告)号：US06229685B1

公开(公告)日：2001-05-08

申请号：US09467734

申请日：1999-12-20

Applicant: Subhas Bothra ,  Dipankar Pramanik ,  Calvin T. Gabriel

Inventor： Subhas Bothra ,  Dipankar Pramanik ,  Calvin T. Gabriel

IPC: H01G4228

CPC classification number: H01L28/60 ,  H01L28/55

Abstract: A capacitor and a method of making the capacitor is provided. The capacitor includes a metallization line with a high dielectric constant layer defined over the metallization line. A thin metallization film is defined over the high dielectric constant layer, such that the thin metallization film defines a top plate of the capacitor, the high dielectric constant layer defines a dielectric for the capacitor, and the metallization line defines a bottom plate for the capacitor. The metallization line is defined from a metallization level and the thin metallization film is defined before a next metallization level above the metallization level is defined.

Abstract translation: 提供电容器和制造电容器的方法。 电容器包括金属化线，其具有限定在金属化线上的高介电常数层。 在高介电常数层上限定薄金属化膜，使得薄金属化膜限定电容器的顶板，高介电常数层限定用于电容器的电介质，并且金属化线限定用于电容器的底板 。 金属化线由金属化水平限定，并且在限定金属化水平以上的下一个金属化水平之前限定薄金属化膜。

公开(公告)号：US06221759B1

公开(公告)日：2001-04-24

申请号：US09100639

申请日：1998-06-19

Applicant: Subhas Bothra ,  Stephen L. Skala

Inventor： Subhas Bothra ,  Stephen L. Skala

IPC: H01L214763

CPC classification number: H01L21/76807

Abstract: Disclosed is a method for forming an aligned via under a trench to prevent voiding in a dual damascene process. The trench is formed in an oxide layer that is formed over a first metal layer and the first metal layer is formed over a semiconductor substrate. The method includes forming an etch stop layer over the oxide layer and forming a set of adjacent trenches in the oxide layer through a portion of the etch stop layer. The method also includes forming a resist layer at least partially over the etch stop layer. The resist layer is formed in a via pattern to expose the set of adjacent trenches through the via pattern. The method further includes etching the oxide layer under the set of adjacent trenches until the oxide layer is etched through to expose at least a portion of the first metal layer so as to form a via under each of the adjacent trenches. In this process, the etch stop layer inhibits the oxide layer underneath from being etched substantially such that each of the vias formed under the each of the adjacent trenches is substantially of a same width as and in alignment with the associated trench above.

Abstract translation: 公开了一种用于在沟槽下形成对准的通孔以防止双镶嵌工艺中的空隙的方法。 沟槽形成在形成在第一金属层上的氧化物层中，并且第一金属层形成在半导体衬底上。 该方法包括在氧化物层上形成蚀刻停止层，并通过蚀刻停止层的一部分在氧化物层中形成一组相邻的沟槽。 该方法还包括至少部分地在蚀刻停止层上形成抗蚀剂层。 抗蚀剂层形成为通孔图案，以通过通孔图案露出该组相邻的沟槽。 该方法还包括蚀刻相邻沟槽组之下的氧化物层，直到蚀刻氧化层以露出第一金属层的至少一部分，以便在每个相邻的沟槽下形成通孔。 在该过程中，蚀刻停止层抑制下面的氧化物层被基本蚀刻，使得形成在每个相邻沟槽之下的每个通孔基本上具有与上述相关沟槽相同的宽度和与之相对应的沟槽的对准。