公开(公告)号：US20240290857A1

公开(公告)日：2024-08-29

申请号：US18656251

申请日：2024-05-06

Applicant: Huawei Digital Power Technologies Co., Ltd.

Inventor： Kimimori HAMADA ,  Fei HU

IPC: H01L29/423 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H02M7/12

CPC classification number: H01L29/4236 ,  H01L29/1608 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7832 ,  H02M7/12

Abstract: A semiconductor device includes an N-type semiconductor substrate, an epitaxial layer, a trench structure, a gate, an interlayer dielectric layer, a source, and a drain. The epitaxial layer includes a first P-type semiconductor region. A bottom of the trench structure is in contact with the first P-type semiconductor region. The trench structure includes a plurality of first trenches and one second trench. The first trenches extend in a first direction. The second trench and each of the plurality of first trenches are disposed in a cross manner and communicate with each other. The interlayer dielectric layer covers the gate and has a contact hole that extends in a second direction. The source is disposed at the interlayer dielectric layer. The source is in contact with the source region through the contact hole and is connected to the first P-type semiconductor region.

公开(公告)号：US20240347613A1

公开(公告)日：2024-10-17

申请号：US18642385

申请日：2024-04-22

Applicant: Huawei Digital Power Technologies Co., Ltd.

Inventor： Kimimori HAMADA ,  Fei HU

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/4236 ,  H01L21/02293 ,  H01L21/823418 ,  H01L29/66712 ,  H01L29/7813 ,  H01L29/78696

Abstract: A semiconductor device includes an N-type semiconductor substrate, an epitaxial layer, a trench structure, a gate, an interlayer dielectric layer, a source, and a drain. The trench structure is disposed at the epitaxial layer. The trench structure includes a plurality of first trenches and one second trench. The plurality of first trenches extend in a first direction and are arranged at intervals in a second direction. The second trench extends in the second direction. The second trench and each of the plurality of first trenches are disposed in a cross manner and communicate with each other. The interlayer dielectric layer covers the gate, and has a contact hole that extends in the second direction. The source is disposed at the interlayer dielectric layer, and is in contact, through the contact hole, with the epitaxial layer.

公开(公告)号：US20240274657A1

公开(公告)日：2024-08-15

申请号：US18642452

申请日：2024-04-22

Applicant: Huawei Digital Power Technologies Co., Ltd.

Inventor： Kimimori HAMADA ,  Fei HU

IPC: H01L29/06 ,  B60L53/22 ,  H01L21/04 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/063 ,  H01L21/047 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7813 ,  B60L53/22 ,  B60L2210/10 ,  B60L2210/30

Abstract: A semiconductor device includes an N-type semiconductor substrate, a first epitaxial layer, a plurality of gate trenches disposed at intervals, a gate, an interlayer dielectric layer, a source, and a drain. The plurality of gate trenches are disposed at the first epitaxial layer. The gate includes a first gate and a second gate that are in contact with each other. The first gate is filled in the gate trench. The second gate is disposed on top of the first epitaxial layer. The interlayer dielectric layer covers a side that is of the gate and that is away from the semiconductor substrate, and has contact holes that extend in a second direction. The source is disposed on a side that is of the interlayer dielectric layer and that is away from the semiconductor substrate, and is in contact with the first epitaxial layer through the contact hole.

公开(公告)号：US20240321950A1

公开(公告)日：2024-09-26

申请号：US18732351

申请日：2024-06-03

Applicant: Huawei Digital Power Technologies Co., Ltd.

Inventor： Kimimori HAMADA ,  Fei HU

IPC: H01L29/06 ,  B60L15/00 ,  H01L21/04 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/063 ,  H01L21/047 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7813 ,  B60L15/007 ,  B60L2210/10

Abstract: A semiconductor device includes an N-type semiconductor substrate, a first epitaxial layer, a plurality of gate trenches disposed at intervals, a first gate, a second gate, an interlayer dielectric layer, a source, and a drain. The first epitaxial layer includes a plurality of first P-type semiconductor regions. The first P-type semiconductor region is disposed below the gate trench. The first gate is filled and disposed in the gate trench. The second gate is disposed on top of the first epitaxial layer. The interlayer dielectric layer covers a side that is of the gate and that is away from the semiconductor substrate, and has contact holes that extend in a second direction. The source is disposed on a side that is of the interlayer dielectric layer and that is away from the semiconductor substrate, and is in contact with the first epitaxial layer through the contact hole.