公开(公告)号：US11303334B2

公开(公告)日：2022-04-12

申请号：US17039345

申请日：2020-09-30

Applicant: Huawei Technologies Co., Ltd.

Inventor： Danpu Liu ,  Hao Yan ,  Feng Yu

IPC: H04B7/02 ,  H04L1/02 ,  H04B7/06

Abstract: A communication method and a related device are described. A base station includes a plurality of antenna arrays and a baseband processing unit. The plurality of antenna arrays are distributed around a communication area and are all connected to the baseband processing unit. A terminal in the communication area is configured to perform signal transmission with the antenna arrays, to implement communication with the baseband processing unit. When an obstacle exists between the terminal and a primary antenna array performing signal transmission with the terminal, controlling, by the base station through the baseband processing unit, a secondary antenna array to perform signal transmission with the terminal.

公开(公告)号：US10693481B2

公开(公告)日：2020-06-23

申请号：US16256477

申请日：2019-01-24

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Hao Yan ,  Jiale Huang ,  Lei Lu

IPC: H03L7/06 ,  H03L7/08 ,  G04F8/00 ,  G04F10/00 ,  H03M1/00 ,  H03M1/50 ,  H03L7/081

Abstract: A time-to-digital converter includes N stages of converting circuits, where N2, and N is an integer. Each stage of the converting circuit includes a first delayer and an arbiter; an output end of the first delayer in each stage of the converting circuit outputs a delayed signal of the stage of the converting circuit; and the arbiter in each stage of the converting circuit receives a sampling clock and the delayed signal of the stage of the converting circuit, and compares the sampling clock with the delayed signal to obtain an output signal of the stage of the converting circuit. The first delayer in each stage of the converting circuit includes at least one first delay cell circuit with a first time unit. The first delayer in any stage of the converting circuit includes a less number of first delay cell circuits than the first delayer in a next stage of the converting circuit.

公开(公告)号：US10230383B2

公开(公告)日：2019-03-12

申请号：US15685447

申请日：2017-08-24

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Hao Yan ,  Jiale Huang ,  Lei Lu

IPC: H03M1/50 ,  H03M1/00 ,  G04F10/00 ,  H03L7/081

Abstract: A time-to-digital converter including N stages of converting circuits, where N≥2, and N is an integer. Each stage of converting circuit includes a first delayer and an arbiter; an output end of the first delayer in each stage of converting circuit outputs a delayed signal of the stage of converting circuit; and the arbiter in each stage of converting circuit receives a sampling clock and the delayed signal of the stage of converting circuit, and compares the sampling clock with the delayed signal to obtain an output signal of the stage of converting circuit. Output signals of the N stages of converting circuits form a non-linear binary number, to indicate a time difference between a clock signal and a reference signal.