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公开(公告)号：US20120307545A1
公开(公告)日：2012-12-06
申请号：US13150885
申请日：2011-06-01
IPC分类号： G11C11/22
CPC分类号： G11C11/221
摘要： A ferroelectric memory with interleaved pairs of ferroelectric memory cells of the two-transistor, two-capacitor (2T2C) type. Each memory cell in a given pair is constructed as first and second portions, each portion including a transistor and a ferroelectric capacitor. Within each pair, a first portion of a second memory cell is physically located between the first and second portions of the first memory cell. As a result, complementary bit lines for adjacent columns are interleaved with one another. Each sense amplifier is associated with a multiplexer, so that the adjacent columns of the interleaved memory cells are supported by a single sense amplifier. Noise coupling among the bit lines is reduced, and the sense amplifiers can be placed along one side of the array, reducing the number of dummy cells required to eliminate edge cell effects.
摘要翻译： 具有双晶体管，双电容器（2T2C）型的交错成对的铁电存储器单元的铁电存储器。 给定对中的每个存储单元被构造为第一和第二部分，每个部分包括晶体管和铁电电容器。 在每对内，第二存储单元的第一部分物理地位于第一存储单元的第一和第二部分之间。 结果，用于相邻列的互补位线彼此交错。 每个读出放大器与复用器相关联，使得交错存储器单元的相邻列由单个读出放大器支持。 位线之间的噪声耦合减少，并且读出放大器可以沿着阵列的一侧放置，减少了消除边缘单元效应所需的虚拟单元的数量。
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公开(公告)号：US08416598B2
公开(公告)日：2013-04-09
申请号：US12781601
申请日：2010-05-17
IPC分类号： G11C11/22
摘要： Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.
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公开(公告)号：US08071430B2
公开(公告)日：2011-12-06
申请号：US12975098
申请日：2011-01-14
IPC分类号： H01L21/56
CPC分类号： H01L23/3135 , H01L23/562 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48465 , H01L2224/49175 , H01L2924/19041 , H01L2924/00014 , H01L2924/00
摘要： An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer.
摘要翻译： 一种具有包含F-RAM电路的半导体管芯，模具化合物和至少部分地位于半导体管芯和模具化合物之间的应力缓冲层的F-RAM封装。 此外，制造F-RAM封装的方法包括提供包含F-RAM电路的半导体管芯，在半导体管芯上形成图案化的应力缓冲层，以及形成耦合到应力缓冲层的模具化合物。
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公开(公告)号：US20100309711A1
公开(公告)日：2010-12-09
申请号：US12856279
申请日：2010-08-13
IPC分类号： G11C11/22
CPC分类号： G11C7/065 , G11C11/22 , G11C2207/063
摘要： A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing a current mirror sense amp. A method of reading data from and restoring data back into F-RAM cells in a 1T1C F-RAM device.
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公开(公告)号：US20100302834A1
公开(公告)日：2010-12-02
申请号：US12856305
申请日：2010-08-13
IPC分类号： G11C11/22
CPC分类号： G11C7/065 , G11C11/22 , G11C2207/063
摘要： A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing a current mirror sense amp. A method of reading data from and restoring data back into F-RAM cells in a 1T1C F-RAM device.
摘要翻译： 包含电流镜感应放大器的F-RAM存储器件。 包含耦合到负电压发生器的电流镜检测放大器的F-RAM存储器件。 一种在包含电流镜像放大器的2T2C F-RAM器件中读取数据并将数据恢复回F-RAM单元的方法。 从1T1C F-RAM设备读取数据并将数据恢复回F-RAM单元的方法。
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公开(公告)号：US20100195368A1
公开(公告)日：2010-08-05
申请号：US12362972
申请日：2009-01-30
CPC分类号： G11C7/065 , G11C11/22 , G11C2207/063
摘要： A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing a current mirror sense amp. A method of reading data from and restoring data back into F-RAM cells in a 1T1C F-RAM device.
摘要翻译： 包含电流镜感应放大器的F-RAM存储器件。 包含耦合到负电压发生器的电流镜检测放大器的F-RAM存储器件。 在包含电流镜像放大器的2T2C F-RAM器件中读取数据并将数据恢复回F-RAM单元的方法。 从1T1C F-RAM设备读取数据并将数据恢复回F-RAM单元的方法。
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公开(公告)号：US20090321964A1
公开(公告)日：2009-12-31
申请号：US12396976
申请日：2009-03-03
CPC分类号： H01L23/3135 , H01L23/562 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48465 , H01L2224/49175 , H01L2924/19041 , H01L2924/00014 , H01L2924/00
摘要： An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer.
摘要翻译： 一种具有包含F-RAM电路的半导体管芯，模具化合物和至少部分地位于半导体管芯和模具化合物之间的应力缓冲层的F-RAM封装。 此外，制造F-RAM封装的方法包括提供包含F-RAM电路的半导体管芯，在半导体管芯上形成图案化的应力缓冲层，以及形成耦合到应力缓冲层的模具化合物。
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公开(公告)号：US06667896B2
公开(公告)日：2003-12-23
申请号：US10154647
申请日：2002-05-24
申请人： Juergen T. Rickes , Hugh P. McAdams , James W. Grace , Scott R. Summerfelt , Ralph H. R. Lanham
发明人： Juergen T. Rickes , Hugh P. McAdams , James W. Grace , Scott R. Summerfelt , Ralph H. R. Lanham
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： An integrated circuit device includes a two-dimensional array of ferroelectric memory cells in which plate lines within the array are grouped. The grouping of plate lines accommodates the use of larger plate line drivers, such as CMOS driver inverters. Each plate line group may include some but not all of the rows of memory cells and some but not all of the columns of memory cells within the array.
摘要翻译： 集成电路器件包括阵列内的板状线分组的铁电存储器单元的二维阵列。 板线的分组适应于使用较大的板线驱动器，例如CMOS驱动器反相器。 每个板线组可以包括存储器单元的一些但不是全部行，以及阵列内的一些但不是全部存储单元的列。
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公开(公告)号：US08441833B2
公开(公告)日：2013-05-14
申请号：US13445076
申请日：2012-04-12
IPC分类号： G11C11/22
摘要： Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.
摘要翻译： 构建用于可靠性筛选的非易失性锁存电路，例如在存储器单元和触发器中。 非易失性锁存电路各自包括耦合到存储节点的铁电电容器，例如在交叉耦合的反相器的输出端。 单独的板线连接到互补存储节点的铁电电容器。 通过在存储节点设置逻辑状态，然后通过极化将状态编程到铁电电容器中来执行锁存稳定裕度的时间零测试。 掉电后，电路板以相对于彼此的差分电压偏置，然后锁存器上电以尝试调用编程状态。 差分电压会干扰召回，并提供信号余量的测量及其后期寿命的可靠性。
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公开(公告)号：US20120195096A1
公开(公告)日：2012-08-02
申请号：US13445076
申请日：2012-04-12
IPC分类号： G11C11/22
摘要： Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.
摘要翻译： 构建用于可靠性筛选的非易失性锁存电路，例如在存储器单元和触发器中。 非易失性锁存电路各自包括耦合到存储节点的铁电电容器，例如在交叉耦合的反相器的输出端。 单独的板线连接到互补存储节点的铁电电容器。 通过在存储节点设置逻辑状态，然后通过极化将状态编程到铁电电容器中来执行锁存稳定裕度的时间零测试。 掉电后，电路板以相对于彼此的差分电压偏置，然后锁存器上电以尝试调用编程状态。 差分电压会干扰召回，并提供信号余量的测量及其后期寿命的可靠性。
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