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    FeRAM with a single access/multiple-comparison operation
    2.
    发明授权
    FeRAM with a single access/multiple-comparison operation 失效
    FeRAM具有单次访问/多重比较操作

    公开(公告)号：US06704218B2

    公开(公告)日：2004-03-09

    申请号：US10115753

    申请日：2002-04-02

    申请人： Juergen T. Rickes ,  Hugh P. McAdams ,  James W. Grace

    发明人： Juergen T. Rickes ,  Hugh P. McAdams ,  James W. Grace

    IPC分类号： G11C1122

    CPC分类号： G11C11/22 ,  H01L27/0688

    摘要： A comparator-type sense amplifier compares a constant voltage that was read out of a FeRAM cell to a sequence of reference voltage levels. A multiple-comparison operation includes (a) reading out data to a bit line, (b) applying a first/next reference voltage, (c) comparing the bit line voltage to the applied reference voltage, and (d) repeating steps (b) and (c) one or more times. The multiple comparison operation can be used to characterize operation of an FeRAM cell, predict or detect an FeRAM cell that may introduce a bit error, or to read a multi-bit value from an FeRAM cell.

    摘要翻译： 比较器型读出放大器将从FeRAM单元读出的恒定电压与参考电压电平序列进行比较。 多比较操作包括（a）将数据读出到位线，（b）施​​加第一/下一个参考电压，（c）将位线电压与施加的参考电压进行比较，以及（d）重复步骤 ）和（c）一次或多次。 可以使用多重比较操作来表征FeRAM单元的操作，预测或检测可能引入位错误的FeRAM单元，或者从FeRAM单元读取多位值。

    On-chip charge distribution measurement circuit
    3.
    发明授权
    On-chip charge distribution measurement circuit 失效
    片上电荷分布测量电路

    公开(公告)号：US06590799B1

    公开(公告)日：2003-07-08

    申请号：US10158279

    申请日：2002-05-29

    申请人： Juergen T. Rickes ,  Hugh P. McAdams ,  James W. Grace ,  John Y. Fong ,  Ralph H. Lanham

    发明人： Juergen T. Rickes ,  Hugh P. McAdams ,  James W. Grace ,  John Y. Fong ,  Ralph H. Lanham

    IPC分类号： G11C1122

    CPC分类号： G11C29/028 ,  G11C11/22 ,  G11C29/12005 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/2602 ,  G11C2029/5002

    摘要： A method and circuit for measuring a charge distribution for readout from FeRAM cells is fast enough for an on-chip defect detection and parameter adjustment. A comparator-type sense amplifier and a reference voltage generator measure a bit line charge or voltage using one readout of charge from an FeRAM cell and comparisons of the resulting bit line voltage to a series of reference voltages. A series of result signals from the sense amplifier indicates when the bit line voltage is approximately equal to the reference voltage. The results signals can be output for analysis and/or used internally for defect detection or setting of operating parameters such as a reference used during read operations.

    摘要翻译： 用于测量从FeRAM单元读出的电荷分布的方法和电路足够快以进行片上缺陷检测和参数调整。 比较器型读出放大器和参考电压发生器使用来自FeRAM单元的一次读出电荷测量位线电荷或电压，并将所得位线电压与一系列参考电压进行比较。 来自读出放大器的一系列结果信号指示位线电压何时近似等于参考电压。 结果信号可以输出用于分析和/或内部使用，用于缺陷检测或设置操作参数，例如在读取操作期间使用的参考。

    Accelerated fatigue testing
    4.
    发明授权
    Accelerated fatigue testing 有权
    加速疲劳试验

    公开(公告)号：US06735106B2

    公开(公告)日：2004-05-11

    申请号：US10190102

    申请日：2002-07-02

    申请人： Juergen T. Rickes ,  Hugh P. McAdams ,  James W. Grace ,  John Y. Fong ,  Ralph H. Lanham

    发明人： Juergen T. Rickes ,  Hugh P. McAdams ,  James W. Grace ,  John Y. Fong ,  Ralph H. Lanham

    IPC分类号： G11C1122

    CPC分类号： G11C29/50 ,  G11C11/22 ,  G11C2029/5002

    摘要： A memory such as a FeRAM implements accelerated fatigue operations that simultaneously change the storage state of large numbers of memory cells and can be rapidly repeated. In one embodiment, the FeRAM includes multiple segments with plate lines in each segment being isolated from plate lines in other segments. A first fatigue operation uses standard read/write decoding for word lines but simultaneously activates all segments. A second fatigue operation activates all segments and all plate lines and exercises one row of memory cells in each plate line group. A third fatigue operation is similar to the second but cycles through rows in the plate line groups so that a number of repetitions of the third fatigue operation equally fatigue every FeRAM cell.

    摘要翻译： 诸如FeRAM的存储器实现加速疲劳操作，其同时改变大量存储器单元的存储状态并且可以快速重复。 在一个实施例中，FeRAM包括多个段，每个段中的板线与其它段中的板线隔离。 第一次疲劳操作使用字线的标准读/写解码，但同时激活所有段。 第二次疲劳操作激活所有的段和所有的板条，并在每个板组组中锻炼一行记忆单元。 第三个疲劳操作类似于第二个但是在板组组中的行循环，使得第三疲劳操作的重复次数对于每个FeRAM单元同样疲劳。

    On-chip compression of charge distribution data
    5.
    发明授权
    On-chip compression of charge distribution data 有权

    公开(公告)号：US06714469B2

    公开(公告)日：2004-03-30

    申请号：US10190370

    申请日：2002-07-02

    申请人： Juergen T. Rickes ,  Hugh P. McAdams

    发明人： Juergen T. Rickes ,  Hugh P. McAdams

    IPC分类号： G11C2900

    CPC分类号： G11C7/1012 ,  G11C7/1006 ,  G11C11/22 ,  G11C29/40

    摘要： A method and circuit for measuring a charge distribution for readout from a memory such as a FeRAM uses on-chip compression of bit line voltage measurements. One embodiment includes a compression circuit coupled to sense amplifiers. Each sense amplifier compares a series of reference voltages to a corresponding bit line and sets a result value for the comparison. A series of result values from a sense amplifier has a transition when the bit line voltage is approximately equal to the reference voltage. The compression circuit can use the transition as a trigger to record a compressed value indicating the reference voltage at the transition.

    Dynamic reference voltage calibration integrated FeRAMS
    6.
    发明授权
    Dynamic reference voltage calibration integrated FeRAMS 有权
    动态参考电压校准集成了FeRAMS

    公开(公告)号：US06804141B1

    公开(公告)日：2004-10-12

    申请号：US10442360

    申请日：2003-05-20

    申请人： Juergen T. Rickes ,  Yacoub Mustafa ,  Hugh P. McAdams

    发明人： Juergen T. Rickes ,  Yacoub Mustafa ,  Hugh P. McAdams

    IPC分类号： G11C1112

    CPC分类号： G11C11/22 ,  G11C2207/2254

    摘要： A FeRAM includes a reference voltage calibration circuit that evaluates FeRAM cells and selects reference voltages for reading the FeRAM cells. Calibration of the reference voltage can be performed dynamically during normal operation of the FeRAM so that the reference voltage tracks changes in FeRAM cell performance that may be associated with temperature or aging effects. Dynamic calibration during normal use eliminates the need for a reference voltage calibration process during manufacture of the memory. The calibration circuit can further be connected to redundancy circuitry that replaces FeRAM cells that the calibration circuit determines are weak.

    摘要翻译： FeRAM包括评估FeRAM单元并选择用于读取FeRAM单元的参考电压的参考电压校准电路。 参考电压的校准可以在FeRAM的正常操作期间动态执行，以使参考电压跟踪可能与温度或老化影响相关的FeRAM单元性能的变化。 正常使用期间的动态校准消除了在存储器制造期间对参考电压校准过程的需要。 校准电路还可以连接到替代校准电路确定的FeRAM单元较弱的冗余电路。

    Interleaved Bit Line Architecture for 2T2C Ferroelectric Memories
    9.
    发明申请
    Interleaved Bit Line Architecture for 2T2C Ferroelectric Memories 审中-公开
    2T2C铁电存储器的交错位线架构

    公开(公告)号：US20120307545A1

    公开(公告)日：2012-12-06

    申请号：US13150885

    申请日：2011-06-01

    申请人： Hugh P. McAdams ,  Scott R. Summerfelt ,  Patrick M. Ndai

    发明人： Hugh P. McAdams ,  Scott R. Summerfelt ,  Patrick M. Ndai

    IPC分类号： G11C11/22

    CPC分类号： G11C11/221

    摘要： A ferroelectric memory with interleaved pairs of ferroelectric memory cells of the two-transistor, two-capacitor (2T2C) type. Each memory cell in a given pair is constructed as first and second portions, each portion including a transistor and a ferroelectric capacitor. Within each pair, a first portion of a second memory cell is physically located between the first and second portions of the first memory cell. As a result, complementary bit lines for adjacent columns are interleaved with one another. Each sense amplifier is associated with a multiplexer, so that the adjacent columns of the interleaved memory cells are supported by a single sense amplifier. Noise coupling among the bit lines is reduced, and the sense amplifiers can be placed along one side of the array, reducing the number of dummy cells required to eliminate edge cell effects.

    摘要翻译： 具有双晶体管，双电容器（2T2C）型的交错成对的铁电存储器单元的铁电存储器。 给定对中的每个存储单元被构造为第一和第二部分，每个部分包括晶体管和铁电电容器。 在每对内，第二存储单元的第一部分物理地位于第一存储单元的第一和第二部分之间。 结果，用于相邻列的互补位线彼此交错。 每个读出放大器与复用器相关联，使得交错存储器单元的相邻列由单个读出放大器支持。 位线之间的噪声耦合减少，并且读出放大器可以沿着阵列的一侧放置，减少了消除边缘单元效应所需的虚拟单元的数量。