-
1.发明授权System and method of using academic analytics of institutional data to improve student success 有权使用机构数据的学术分析来提高学生成功的系统和方法公开(公告)号：US08412736B1
公开(公告)日：2013-04-02
申请号：US12911310
申请日：2010-10-25
CPC分类号： G06F17/30539 , G06Q10/00
摘要： Systems and methods that extend the use of data mining to identify students academically at risk of performing poorly or withdrawing from school altogether. In doing so, academically at-risk students are identified early and guided to resources to improve their academic performance.
摘要翻译： 扩大数据挖掘的使用的系统和方法，以确定学生在学业上表现不佳或退学的风险。 在这样做的时候，学术风险较高的学生早期被识别，并引导资源来提高他们的学业成绩。
-
公开(公告)号：US08071430B2
公开(公告)日：2011-12-06
申请号：US12975098
申请日：2011-01-14
IPC分类号： H01L21/56
CPC分类号： H01L23/3135 , H01L23/562 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48465 , H01L2224/49175 , H01L2924/19041 , H01L2924/00014 , H01L2924/00
摘要： An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer.
摘要翻译： 一种具有包含F-RAM电路的半导体管芯，模具化合物和至少部分地位于半导体管芯和模具化合物之间的应力缓冲层的F-RAM封装。 此外，制造F-RAM封装的方法包括提供包含F-RAM电路的半导体管芯，在半导体管芯上形成图案化的应力缓冲层，以及形成耦合到应力缓冲层的模具化合物。
-
公开(公告)号：US20090321964A1
公开(公告)日：2009-12-31
申请号：US12396976
申请日：2009-03-03
CPC分类号： H01L23/3135 , H01L23/562 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48465 , H01L2224/49175 , H01L2924/19041 , H01L2924/00014 , H01L2924/00
摘要： An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer.
摘要翻译： 一种具有包含F-RAM电路的半导体管芯，模具化合物和至少部分地位于半导体管芯和模具化合物之间的应力缓冲层的F-RAM封装。 此外，制造F-RAM封装的方法包括提供包含F-RAM电路的半导体管芯，在半导体管芯上形成图案化的应力缓冲层，以及形成耦合到应力缓冲层的模具化合物。
-
公开(公告)号：US5602773A
公开(公告)日：1997-02-11
申请号：US477845
申请日：1995-06-07
申请人： John P. Campbell
发明人： John P. Campbell
CPC分类号： G11C7/18
摘要： A semiconductor memory device (20) includes N bitlines (31, 32, 33, 34) addressable by a partially decoded column address, wherein N is greater two. A column address selection lead (YSEL) has plural segments, each of which overlays a length of one of the bitlines. Each segment of the column address selection lead overlays no more than approximately 1/N of the length of a bitline. Adjacent column address selection leads are separated by approximately the pitch of N-1 bitlines.
摘要翻译： 半导体存储器件（20）包括可通过部分解码的列地址寻址的N位线（31,32,33,34），其中N大于2。 列地址选择引线（YSEL）具有多个段，每个段与位线之一的长度重叠。 列地址选择引线的每个段覆盖不超过位线长度的大约1 / N。 相邻列地址选择引线以大约N-1位线的间距分开。
-
公开(公告)号：US5485419A
公开(公告)日：1996-01-16
申请号：US247914
申请日：1994-05-23
申请人： John P. Campbell
发明人： John P. Campbell
CPC分类号： G11C7/18
摘要： A semiconductor memory device (20) includes N bitlines (31, 32, 33, 34) addressable by a partially decoded column address, wherein N is greater two. A column address selection lead (YSEL) has plural segments, each of which overlays a length of one of the bitlines. Each segment of the column address selection lead overlays no more than approximately 1/N of the length of a bitline. Adjacent column address selection leads are separated by approximately the pitch of N-1 bitlines.
摘要翻译： 半导体存储器件（20）包括可通过部分解码的列地址寻址的N位线（31,32,33,34），其中N大于2。 列地址选择引线（YSEL）具有多个段，每个段与位线之一的长度重叠。 列地址选择引线的每个段覆盖不超过位线长度的大约1 / N。 相邻列地址选择引线以大约N-1位线的间距分开。
-
公开(公告)号：US07323409B2
公开(公告)日：2008-01-29
申请号：US11053313
申请日：2005-02-07
IPC分类号： H01L21/768
CPC分类号： H01L21/76843 , H01L21/7685 , H01L21/76858 , H01L21/76871 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier layer, and the via structure include a seed layer, a diffusion barrier layer and a metal plug.The via seed layer is controlled to a thickness that discourages the reaction between the via seed layer and the bulk conductor layer. The reaction may result in the formation of harmful voids at the bottom of the vias and is caused by having the via seed metal coming in contact with the bulk conductor through openings in the barrier layer.
摘要翻译： 描述了多层金属和通孔结构。 金属导体包括基底或种子层，体导体层，覆盖层和阻挡层，并且通孔结构包括种子层，扩散阻挡层和金属插塞。 通孔种子层被控制到阻止通孔种子层和体导体层之间的反应的厚度。 反应可能导致在通孔底部形成有害空隙，并且是由于通孔种子金属通过阻挡层中的开口与体导体接触而引起的。
-
公开(公告)号：US06977437B2
公开(公告)日：2005-12-20
申请号：US10385824
申请日：2003-03-11
IPC分类号： H01L21/768 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76843 , H01L21/7685 , H01L21/76858 , H01L21/76871 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A multilevel metal and via structure is described. The metal conductors include a base or seed layer, a bulk conductor layer, a capping layer, and a barrier layer, and the via structure include a seed layer, a diffusion barrier layer and a metal plug. The via seed layer is controlled to a thickness that discourages the reaction between the via seed layer and the bulk conductor layer. The reaction may result in the formation of harmful voids at the bottom of the vias and is caused by having the via seed metal coming in contact with the bulk conductor through openings in the barrier layer.
-
公开(公告)号：US08058677B2
公开(公告)日：2011-11-15
申请号：US12396976
申请日：2009-03-03
IPC分类号： H01L23/28
CPC分类号： H01L23/3135 , H01L23/562 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48465 , H01L2224/49175 , H01L2924/19041 , H01L2924/00014 , H01L2924/00
摘要： An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer.
-
公开(公告)号：US20080207006A1
公开(公告)日：2008-08-28
申请号：US11680340
申请日：2007-02-28
申请人： James Scott Martin , John P. Campbell , Phuong-Lan Tran , Alfred J. Griffin , Maxwell Walthour Lippitt
发明人： James Scott Martin , John P. Campbell , Phuong-Lan Tran , Alfred J. Griffin , Maxwell Walthour Lippitt
IPC分类号： H01L21/469
CPC分类号： H01L21/28556 , H01L21/76843 , H01L21/76862
摘要： The present disclosure is directed to a process for plasma treating a film comprising titanium, nitrogen and impurities on a substrate. The process comprises forming a plasma of nitrogen gas and hydrogen gas, the flow ratio of hydrogen gas to nitrogen gas ranging from about 0.01 to about 0.7. The film is contacted with the plasma for a time sufficient to reduce the concentration of impurities in the film.
摘要翻译： 本公开涉及用于在基底上等离子体处理包含钛，氮和杂质的膜的方法。 该方法包括形成氮气和氢气的等离子体，氢气与氮气的流量比为约0.01至约0.7。 膜与等离子体接触足以减少膜中杂质浓度的时间。
-
公开(公告)号：US1156612A
公开(公告)日：1915-10-12
申请号：US1914875472
申请日：1914-12-04
申请人： JOHN P CAMPBELL
发明人： MORRELL LON
CPC分类号： B05B3/0445
-
-
-
-
-
-
-
-
-
搜索结果
11 条记录 (耗时 0.015 秒)
