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公开(公告)号：US08441833B2
公开(公告)日：2013-05-14
申请号：US13445076
申请日：2012-04-12
IPC分类号： G11C11/22
摘要： Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.
摘要翻译： 构建用于可靠性筛选的非易失性锁存电路，例如在存储器单元和触发器中。 非易失性锁存电路各自包括耦合到存储节点的铁电电容器，例如在交叉耦合的反相器的输出端。 单独的板线连接到互补存储节点的铁电电容器。 通过在存储节点设置逻辑状态，然后通过极化将状态编程到铁电电容器中来执行锁存稳定裕度的时间零测试。 掉电后，电路板以相对于彼此的差分电压偏置，然后锁存器上电以尝试调用编程状态。 差分电压会干扰召回，并提供信号余量的测量及其后期寿命的可靠性。
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公开(公告)号：US20120195096A1
公开(公告)日：2012-08-02
申请号：US13445076
申请日：2012-04-12
IPC分类号： G11C11/22
摘要： Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.
摘要翻译： 构建用于可靠性筛选的非易失性锁存电路，例如在存储器单元和触发器中。 非易失性锁存电路各自包括耦合到存储节点的铁电电容器，例如在交叉耦合的反相器的输出端。 单独的板线连接到互补存储节点的铁电电容器。 通过在存储节点设置逻辑状态，然后通过极化将状态编程到铁电电容器中来执行锁存稳定裕度的时间零测试。 掉电后，电路板以相对于彼此的差分电压偏置，然后锁存器上电以尝试调用编程状态。 差分电压会干扰召回，并提供信号余量的测量及其后期寿命的可靠性。
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公开(公告)号：US20100296329A1
公开(公告)日：2010-11-25
申请号：US12781601
申请日：2010-05-17
摘要： Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.
摘要翻译： 构建用于可靠性筛选的非易失性锁存电路，例如在存储器单元和触发器中。 非易失性锁存电路各自包括耦合到存储节点的铁电电容器，例如在交叉耦合的反相器的输出端。 单独的板线连接到互补存储节点的铁电电容器。 通过在存储节点设置逻辑状态，然后通过极化将状态编程到铁电电容器中来执行锁存稳定裕度的时间零测试。 掉电后，电路板以相对于彼此的差分电压偏置，然后锁存器上电以尝试调用编程状态。 差分电压会干扰召回，并提供信号余量的测量及其后期寿命的可靠性。
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公开(公告)号：US08416598B2
公开(公告)日：2013-04-09
申请号：US12781601
申请日：2010-05-17
IPC分类号： G11C11/22
摘要： Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.
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公开(公告)号：US20120307545A1
公开(公告)日：2012-12-06
申请号：US13150885
申请日：2011-06-01
IPC分类号： G11C11/22
CPC分类号： G11C11/221
摘要： A ferroelectric memory with interleaved pairs of ferroelectric memory cells of the two-transistor, two-capacitor (2T2C) type. Each memory cell in a given pair is constructed as first and second portions, each portion including a transistor and a ferroelectric capacitor. Within each pair, a first portion of a second memory cell is physically located between the first and second portions of the first memory cell. As a result, complementary bit lines for adjacent columns are interleaved with one another. Each sense amplifier is associated with a multiplexer, so that the adjacent columns of the interleaved memory cells are supported by a single sense amplifier. Noise coupling among the bit lines is reduced, and the sense amplifiers can be placed along one side of the array, reducing the number of dummy cells required to eliminate edge cell effects.
摘要翻译： 具有双晶体管，双电容器（2T2C）型的交错成对的铁电存储器单元的铁电存储器。 给定对中的每个存储单元被构造为第一和第二部分，每个部分包括晶体管和铁电电容器。 在每对内，第二存储单元的第一部分物理地位于第一存储单元的第一和第二部分之间。 结果，用于相邻列的互补位线彼此交错。 每个读出放大器与复用器相关联，使得交错存储器单元的相邻列由单个读出放大器支持。 位线之间的噪声耦合减少，并且读出放大器可以沿着阵列的一侧放置，减少了消除边缘单元效应所需的虚拟单元的数量。
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公开(公告)号：US08071430B2
公开(公告)日：2011-12-06
申请号：US12975098
申请日：2011-01-14
IPC分类号： H01L21/56
CPC分类号： H01L23/3135 , H01L23/562 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48465 , H01L2224/49175 , H01L2924/19041 , H01L2924/00014 , H01L2924/00
摘要： An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer.
摘要翻译： 一种具有包含F-RAM电路的半导体管芯，模具化合物和至少部分地位于半导体管芯和模具化合物之间的应力缓冲层的F-RAM封装。 此外，制造F-RAM封装的方法包括提供包含F-RAM电路的半导体管芯，在半导体管芯上形成图案化的应力缓冲层，以及形成耦合到应力缓冲层的模具化合物。
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公开(公告)号：US08058677B2
公开(公告)日：2011-11-15
申请号：US12396976
申请日：2009-03-03
IPC分类号： H01L23/28
CPC分类号： H01L23/3135 , H01L23/562 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48465 , H01L2224/49175 , H01L2924/19041 , H01L2924/00014 , H01L2924/00
摘要： An F-RAM package having a semiconductor die containing F-RAM circuitry, a mold compound, and a stress buffer layer that is at least partially located between the semiconductor die and the mold compound. Also, a method for making an F-RAM package that includes providing a semiconductor die containing F-RAM circuitry, forming a patterned stress buffer layer over the semiconductor die, and forming a mold compound coupled to the stress buffer layer.
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公开(公告)号：US07933138B2
公开(公告)日：2011-04-26
申请号：US12362972
申请日：2009-01-30
IPC分类号： G11C11/22
CPC分类号： G11C7/065 , G11C11/22 , G11C2207/063
摘要： A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing a current mirror sense amp. A method of reading data from and restoring data back into F-RAM cells in a 1T1C F-RAM device.
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公开(公告)号：US07894235B2
公开(公告)日：2011-02-22
申请号：US12856279
申请日：2010-08-13
IPC分类号： G11C11/22
CPC分类号： G11C7/065 , G11C11/22 , G11C2207/063
摘要： A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing a current mirror sense amp. A method of reading data from and restoring data back into F-RAM cells in a 1T1C F-RAM device.
摘要翻译： 包含电流镜感应放大器的F-RAM存储器件。 包含耦合到负电压发生器的电流镜检测放大器的F-RAM存储器件。 一种在包含电流镜像放大器的2T2C F-RAM器件中读取数据并将数据恢复回F-RAM单元的方法。 从1T1C F-RAM设备读取数据并将数据恢复回F-RAM单元的方法。
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公开(公告)号：US20110019461A1
公开(公告)日：2011-01-27
申请号：US12507449
申请日：2009-07-22
CPC分类号： G11C11/22
摘要： A process of operating an integrated circuit containing a programmable data storage component including at least one data ferroelectric capacitor and at least one additional ferroelectric capacitor, in which power is removed from a state circuit after each read operation. A process of operating an integrated circuit containing a programmable data storage component including at least one data ferroelectric capacitor and at least one additional ferroelectric capacitor, in which power is removed from a state circuit after each write operation. A process of operating an integrated circuit containing a programmable data storage component including four data ferroelectric capacitors, in which power is removed from a state circuit after each read operation and after each write operation.
摘要翻译： 一种操作包含可编程数据存储组件的集成电路的过程，该可编程数据存储组件包括至少一个数据铁电电容器和至少一个额外的铁电电容器，其中在每次读取操作之后从状态电路中去除功率。 一种操作包含可编程数据存储部件的集成电路的过程，该可编程数据存储部件包括至少一个数据铁电电容器和至少一个附加的铁电电容器，其中在每次写入操作之后从状态电路去除功率。 一种操作包含可编程数据存储部件的集成电路的处理，该可编程数据存储部件包括四个数据铁电电容器，其中在每次读取操作之后和每次写入操作之后，从状态电路中去除功率。
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