公开(公告)号：US3619735A

公开(公告)日：1971-11-09

申请号：US3619735D

申请日：1970-01-26

Applicant: IBM

Inventor： CHEN CHARLES Y ,  DHAKA VIR A ,  KROLIKOWSKI WALTER F

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/07 ,  H01L19/00

CPC classification number: H01L27/0794 ,  H01L27/0755 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/151

Abstract: An integrated circuit and process for making it wherein a decoupling capacitor is provided beneath devices in the surface of the integrated circuit by the formation of a first epitaxial layer between an N substrate having a P zone diffused therein and an N device-containing epitaxial layer. A P channel diffusion to the P zone formed in the substrate will serve as a damping resistor in combination with the coupling capacitor. The process for forming such a decoupling capacitor in an integrated circuit comprises, inter alia, diffusing P impurities into the substrate to form a large junction which will subsequently function as a decoupling capacitor. A first intrinsic, P or N epitaxial layer is then grown on the semiconductor substrate. Subsequently, an N epitaxial layer is grown on the first epitaxial layer. A P channel is then driven through the N epitaxial layer and the first epitaxial layer to contact the P diffused zone which serves as the decoupling capacitor. This P channel diffusion will serve as a damping resistor in combination with the decoupling capacitor. Device diffusion, i.e., transistors, resistors, etc., will take place into the N epitaxial layer, and during growth of the epitaxial layers the P zone will significantly outdiffuse into the first epitaxial layer. Appropriate channels, isolations and contacts are also provided.