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    Integrated circuit with buried decoupling capacitor
    5.
    发明授权
    Integrated circuit with buried decoupling capacitor 失效
    集成电路与埋入式电容器

    公开(公告)号：US3619735A

    公开(公告)日：1971-11-09

    申请号：US3619735D

    申请日：1970-01-26

    Applicant: IBM

    Inventor： CHEN CHARLES Y ,  DHAKA VIR A ,  KROLIKOWSKI WALTER F

    IPC: H01L27/04 ,  H01L21/822 ,  H01L27/07 ,  H01L19/00

    CPC classification number: H01L27/0794 ,  H01L27/0755 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/151

    Abstract: An integrated circuit and process for making it wherein a decoupling capacitor is provided beneath devices in the surface of the integrated circuit by the formation of a first epitaxial layer between an N substrate having a P zone diffused therein and an N device-containing epitaxial layer. A P channel diffusion to the P zone formed in the substrate will serve as a damping resistor in combination with the coupling capacitor. The process for forming such a decoupling capacitor in an integrated circuit comprises, inter alia, diffusing P impurities into the substrate to form a large junction which will subsequently function as a decoupling capacitor. A first intrinsic, P or N epitaxial layer is then grown on the semiconductor substrate. Subsequently, an N epitaxial layer is grown on the first epitaxial layer. A P channel is then driven through the N epitaxial layer and the first epitaxial layer to contact the P diffused zone which serves as the decoupling capacitor. This P channel diffusion will serve as a damping resistor in combination with the decoupling capacitor. Device diffusion, i.e., transistors, resistors, etc., will take place into the N epitaxial layer, and during growth of the epitaxial layers the P zone will significantly outdiffuse into the first epitaxial layer. Appropriate channels, isolations and contacts are also provided.

    Metallization process
    6.
    发明授权
    Metallization process 失效
    金属化过程

    公开(公告)号：US3558352A

    公开(公告)日：1971-01-26

    申请号：US3558352D

    申请日：1966-10-27

    Applicant: IBM

    Inventor： CASTRUCCI PAUL P ,  WITT DAVID DE ,  MUTTER WALTER E ,  DHAKA VIR A

    IPC: H01L21/00 ,  H01L21/331 ,  H01L23/485 ,  H01L29/00 ,  H01L1/14 ,  H01L5/02

    CPC classification number: H01L23/485 ,  H01L21/00 ,  H01L29/00 ,  H01L29/66303 ,  H01L2924/0002 ,  Y10S438/951 ,  H01L2924/00

    Abstract: A SEMICONDUCTIVE DEVICE AND A METHOD FOR FORMING A SEMICONDUCTOR DEVICE WHEREIN THE OHMIC CONTACT IS IN THE ORDER OF MICRONS IN WIDTH. A FIRST METAL IS FORMED IN THE OPENING IN THE PROTECTIVE COATING WHICH ACTS AS THE OHMIC CONTACT TO THE SEMICONDUCTOR DEVICE. A SECOND METAL MAY BE APPLIED ONLY OVER THE FIRST METAL BY ELECTROLESS OR ELECTROPLATING TECHNIQUES TO INCREASE THE CONDUCTIVITY OF THE OHMIC CONTACT. FINALLY, AN EXTERNAL LAND METAL LAYER IS DEPOSITED OVER A RELATIVELY LARGE AREA OF THE PROTECTIVE COATING IN THE AREA OF THE OHMIC CONTACT WITH FINGER-LIKE EXTENSIONS OF THE LAND METAL LAYER CONTACTING THE OHMIC CONTACT BY SHORT OVERLAID AREAS. THE EXTERNAL LAND IS THE ONLY METAL LAYER IN THE PROCESS FORMED WHICH REQUIRES A PHOTOGRAPHIC MASK. THE PROCESS, THEREFORE, IN NOT LIMITED BY PRESENT DAY PHOTOENGRAVING TECHNIQUES.

    Process for producing monolithic circuits
    8.
    发明授权
    Process for producing monolithic circuits 失效
    制造单片电路的工艺

    公开(公告)号：US3923562A

    公开(公告)日：1975-12-02

    申请号：US15650471

    申请日：1971-06-24

    Applicant: IBM

    Inventor： DHAKA VIR A

    IPC: H01L21/00 ,  H01L21/316 ,  H01L21/8222 ,  H01L23/29 ,  H01L23/485 ,  H01L21/223

    CPC classification number: H01L23/291 ,  H01L21/00 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/8222 ,  H01L23/29 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S148/043 ,  Y10S148/051 ,  Y10S148/106 ,  H01L2924/00

    Abstract: A technique of fabricating semiconductor devices so as to avoid mask alignment difficulties when it is required that electrical contact be made subsequent to the formation of extremely small device regions. The diffusion mask for creating the small device regions is constituted of a first film which is subject to ready etching by a first etchant but which is substantially unaffected by a second etchant. A second film covers the opening in the device region formation. This film being subject to etching by the second etchant but being substantially unaffected by the first etchant. As a result, the second film is removed from within the opening without affecting the first film since the first film will resist the second etchant. Thus, the original opening is re-established for the purpose of making contact to the device region, the first film remaining as a passivating film on the substrate.

    Abstract translation: 一种制造半导体器件的技术，以便在需要在形成极小的器件区域之后进行电接触时避免掩模对准困难。 用于产生小器件区域的扩散掩模由第一蚀刻剂进行刻蚀，但基本上不受第二蚀刻剂影响的第一膜构成。 第二膜覆盖器件区域形成中的开口。 该薄膜经受第二蚀刻剂的蚀刻，但基本上不受第一蚀刻剂的影响。 结果，由于第一膜将抵抗第二蚀刻剂，所以第二膜从开口内移除而不影响第一膜。 因此，为了与器件区域接触，重新建立原始开口，第一膜作为基板上的钝化膜残留。

    Photochemical fabrication process
    9.
    发明授权
    Photochemical fabrication process 失效
    光化学制造工艺

    公开(公告)号：US3573975A

    公开(公告)日：1971-04-06

    申请号：US3573975D

    申请日：1968-07-10

    Applicant: IBM

    Inventor： DHAKA VIR A ,  CLARK EDWIN R ,  PINCK ARNOLD

    IPC: G03F7/20 ,  G03C5/00

    CPC classification number: G03F7/2041

    Abstract: IN A PHOTOCHEMICAL FABRICATION PROCESS WHEREIN A PHOTORESIST LAYER IS IMAGE-WISE EXPOSED BY CONTACT EXPOSURE THROUGH A MASK, THE IMPROVEMENT OF PROVIDING A LIQUID INTERFACE BETWEEN THE PHOTORESIST LAYER AND MASK PRIOR AND DURING EXPOSURE.

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