公开(公告)号：US3899363A

公开(公告)日：1975-08-12

申请号：US48403374

申请日：1974-06-28

Applicant: IBM

Inventor： DENNARD ROBERT H ,  RIDEOUT VINCENT L ,  WALKER EDWARD J

IPC: H01L27/088 ,  H01L21/00 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/316 ,  H01L21/32 ,  H01L21/331 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/73 ,  H01L29/78 ,  H01L27/08

CPC classification number: H01L21/76216 ,  H01L21/00 ,  H01L21/30608 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/32 ,  H01L21/7621 ,  Y10S148/051

Abstract: Densely packed integrated circuit arrays for high speed memory and logic applications are fabricated using silicon semiconductor field-effect transistors (FET) which are electrically isolated one from the other by fully recessed oxide isolation regions. The method of fabrication is featured by the reduction of detrimental source to drain conduction along the side-wall of the recessed oxide to a level less than that of the main channel of the FET. Ion implantation is used to provide additional doping concentrations in the silicon substrate adjacent to the sidewall region and underneath the recessed oxide. The excess dopant underneath the recessed oxide serves as a parasitic-channel stopper. Sidewall doping is facilitated by implanting into canted sidewalls in the silicon substrate prior to the formation of the recessed oxide therein. The canted side-walls are achieved by utilizing an anisotropic etch in combination with a oriented p-conductivity type substrate.

Abstract translation: 使用硅半导体场效应晶体管（FET）制造用于高速存储器和逻辑应用的紧密集成的集成电路阵列，其通过完全凹陷的氧化物隔离区彼此电隔离。 制造方法的特征在于将凹陷氧化物的侧壁的有害源降低到漏极导通的程度比FET的主沟道的电流更小。 离子注入用于在邻近侧壁区域和凹陷氧化物下面的硅衬底中提供额外的掺杂浓度。 凹陷氧化物下面的多余掺杂剂用作寄生通道阻挡层。 在其中形成凹陷的氧化物之前，通过将硅衬底中的倾斜侧壁植入，来促进侧壁掺杂。 倾斜的侧壁通过利用与<100>取向的p导电型基底组合的各向异性蚀刻来实现。