公开(公告)号：US3577190A

公开(公告)日：1971-05-04

申请号：US3577190D

申请日：1968-06-26

Applicant: IBM

Inventor： COCKE JOHN ,  DAUBER PHILIP S ,  SCHORR HERBERT ,  SUSSENGUTH EDWARD H

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/10

CPC classification number: G06F9/30069

Abstract: Apparatus in a digital computer for allowing the skipping of predetermined instructions in a sequence of instructions is disclosed. Means are provided for detecting a specific type of instruction in a sequence of instructions. This specific type of instruction is referred to as a skip instruction and indicates that upon the occurrence of a specified machine condition, predetermined subsequent instructions in said sequence are to be skipped. Further means are provided to determine the occurrence of the specified machine condition, and to emit an output signal indicative of the occurrence. Means responsive to the output signal effect the skipping of the predetermined instructions.

公开(公告)号：US3670309A

公开(公告)日：1972-06-13

申请号：US3670309D

申请日：1969-12-23

Applicant: IBM

Inventor： AMDAHL GENE M ,  ARNOLD RICHARD F ,  DAUBER PHILIP S ,  FREIMAN CHARLES V ,  ROBELEN RUSSELL J ,  SCHORR HERBERT ,  WIERZBICKI JOHN R

IPC: G06F13/10 ,  G06F12/08 ,  G06F13/18 ,  G11C9/00 ,  G06F13/00

CPC classification number: G06F12/0857 ,  G06F13/18

Abstract: Described is a storage control system for a two-level storage system. The system includes a high-speed storage against which requests for data are processed and a slower, larger-capacity main storage. Requests for data are received in terms of logical addresses. Requests can be received concurrently at a plurality of request ports where they are buffered in request stacks. A tag storage serves as an index to the data currently resident in high-speed storage, and a directory storage acts as an index to data currently in main storage. A sequence interlock generator is included which interlocks requests in the plurality of request stacks to insure that requests to the same storage area are performed in proper sequence to insure data integrity. When a request is serviced, the logical address is transformed into a plurality of physical addresses in high-speed storage. The corresponding tags from the tag storage and the corresponding data from the high-speed storage are concurrently fetched. A comparison is made of the tags with the transformed address to determine whether the requested data is in high-speed storage. Since request to the same storage entity in high-speed storage or tag storage can be made concurrently by all request ports, conflict resolvers are included to resolve conflicts arising from simultaneous requests to either of these two storages. High-speed storage is divided into storage modules capable of simultaneous operation such that requests from the plurality of request ports can be serviced concurrently. If comparison of the tags indicate that the requested data is available, the request is serviced. An interstorage transfer mechanism is included such that if the requested data is not available in high-speed storage, then the data is retrieved from main storage and placed into high-speed storage for subsequent processing of the request. Concurrently with interstorage transfer, processing of other requests from the request ports is permissible. In the replacement of data from main storage to high-speed storage, provision is made for also replacing data from high-speed storage to main storage if such be necessary.

公开(公告)号：US3577189A

公开(公告)日：1971-05-04

申请号：US3577189D

申请日：1969-01-15

Applicant: IBM

Inventor： COCKE JOHN ,  RANDELL BRIAN ,  SCHORR HERBERT ,  SUSSENGUTH EDWARD H

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/00 ,  G06F9/16

CPC classification number: G06F9/3846

Abstract: Apparatus and a method in a digital computer is disclosed for allowing improved program branching from a first instruction sequence to a second instruction sequence. Said apparatus includes means for decoding a branch instruction in said first sequence; means for determining parameters which are to enter into a condition determination, the resolution of which defines whether or not the branch is to be made, means for detecting a specific type instruction in said first sequence subsequent to said branch instruction, said specific type instruction indicative of the point in the first instruction sequence at which the branch is to be made; and means responsive to said detection for ordering instructions from said second instruction sequence to be processed subsequent to the processing of said specific type instruction.