公开(公告)号：US3593299A

公开(公告)日：1971-07-13

申请号：US3593299D

申请日：1967-07-14

Applicant: IBM

Inventor： DRISCOLL GRAHAM C ,  SUSSENGUTH EDWARD H

IPC: G06F13/12 ,  G06F15/00

CPC classification number: G06F13/124

Abstract: An input-output system which is effectively a satellite computer that performs normal input-output functions for other data processing apparatus components, i.e., the central processing unit and peripheral input and output devices; that exercises supervisory control over the aforesaid apparatus components such as by arranging processing task queues and allocating storage space; that buffers transmissions between remote terminals and devices and the central computing units; and that controls periodic diagnostic analyses of the entire data processing apparatus.

公开(公告)号：US3577189A

公开(公告)日：1971-05-04

申请号：US3577189D

申请日：1969-01-15

Applicant: IBM

Inventor： COCKE JOHN ,  RANDELL BRIAN ,  SCHORR HERBERT ,  SUSSENGUTH EDWARD H

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/00 ,  G06F9/16

CPC classification number: G06F9/3846

Abstract: Apparatus and a method in a digital computer is disclosed for allowing improved program branching from a first instruction sequence to a second instruction sequence. Said apparatus includes means for decoding a branch instruction in said first sequence; means for determining parameters which are to enter into a condition determination, the resolution of which defines whether or not the branch is to be made, means for detecting a specific type instruction in said first sequence subsequent to said branch instruction, said specific type instruction indicative of the point in the first instruction sequence at which the branch is to be made; and means responsive to said detection for ordering instructions from said second instruction sequence to be processed subsequent to the processing of said specific type instruction.

公开(公告)号：US3577190A

公开(公告)日：1971-05-04

申请号：US3577190D

申请日：1968-06-26

Applicant: IBM

Inventor： COCKE JOHN ,  DAUBER PHILIP S ,  SCHORR HERBERT ,  SUSSENGUTH EDWARD H

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/10

CPC classification number: G06F9/30069

Abstract: Apparatus in a digital computer for allowing the skipping of predetermined instructions in a sequence of instructions is disclosed. Means are provided for detecting a specific type of instruction in a sequence of instructions. This specific type of instruction is referred to as a skip instruction and indicates that upon the occurrence of a specified machine condition, predetermined subsequent instructions in said sequence are to be skipped. Further means are provided to determine the occurrence of the specified machine condition, and to emit an output signal indicative of the occurrence. Means responsive to the output signal effect the skipping of the predetermined instructions.

公开(公告)号：US3675215A

公开(公告)日：1972-07-04

申请号：US3675215D

申请日：1970-06-29

Applicant: IBM

Inventor： ARNOLD RICHARD F ,  DAUBER PHILIP S ,  SUSSENGUTH EDWARD H

IPC: G06F12/10 ,  G06F9/20

CPC classification number: G06F12/1063 ,  G06F12/1027 ,  G06F2212/652

Abstract: A directory, or index, of variable-sized pages of data for use in a two-level storage system employing virtual addressing, wherein data is stored in a large capacity main storage and retrieved to a smaller, faster buffer storage for processing. If a desired piece of data indicated by a virtual address is not currently resident in buffer storage, the location of the beginning of the page containing that data in main storage is found by searching the directory. Directory addresses for searching the directory are formed by a pseudo-random function of two parameters, the virtual address and a count. Since a larger page-size entry will be addressed statistically more frequently than a smaller page-size entry, a new directory entry for a given page size is made in the first location along its algorithm chain which currently contains either an invalid entry or a smaller page-size entry. Thus, it may be necessary to relocate a smaller page-size entry further down its chain.

Abstract translation: 用于在采用虚拟寻址的两级存储系统中使用的可变大小的数据页面的目录或索引，其中数据存储在大容量主存储器中并且被检索到较小的较快的缓冲存储器中用于处理。 如果由虚拟地址指示的期望的数据片段当前不存在于缓冲存储器中，则通过搜索目录来找到包含主存储器中的该数据的页面开始位置。 用于搜索目录的目录地址由两个参数的伪随机函数形成，即虚拟地址和计数。 由于较大的页面大小的条目将在统计上比较小的页面大小的条目更频繁地被寻址，所以在沿其算法链的第一个位置中，给定给定的页面大小的新的目录条目当前包含无效条目或较小的页面大小条目 页面大小的条目。 因此，可能需要将较小的页面大小的条目进一步向下移动到其链条上。

公开(公告)号：US3559183A

公开(公告)日：1971-01-26

申请号：US3559183D

申请日：1968-02-29

Applicant: IBM

Inventor： SUSSENGUTH EDWARD H

IPC: G06F9/38 ,  G06F7/02

CPC classification number: G06F9/3806 ,  G06F9/3802

Abstract: APPARATUS FOR RECOGNIZING THE OCCURRENCE OF A PARTICULAR INSTRUCTION IN A STREAM OF INSTRUCTIONS AND THEN MODIFYING THAT STREAM OF INSTRUCTIONS IS DISCLOSED. A FETCH REGISTER FOR RECEIVING INSTRUCTIONS FROM A MAIN MEMORY IS PROVIDED. A PREFETCH SEQUENCE CONTROL REGISTER CONTAINING THE ADDRESS OF A PARTICULAR INSTRUCTION, AS WELL AS THE ADDRESS OF THE NEXT INSTRUCTION TO BE FETCHED IS ALSO PROVIDED. A COMPARISON IS CONTINUOUSLY MADE BETWEEN THE INSTRUCTION ADDRESS IN THE FETCH REGISTER AND IN THE PREFETCH SEQUENCE CONTROL REGISTER. UPON NOTING EQUALITY BETWEEN THOSE TWO, THE SECOND ADDRESS FROM THE PREFETCH SEQUENCE CONTROL REGISTER IS TRANSFERRED TO THE FETCH REGISTER AND THE INSTRUCTION EXTRACTED FROM MEMORY.

MEANS ARE ALSO PROVIDED FOR INHIBITING THIS OPERATION AND PROVIDING AN ADDRESS FROM A RELATED REGISTER TO THE FETCH REGISTER UPON THE OCCURRENCE OF AN EQUALITY BETWEEN THE ADDRESS IN THE FETCH SEQUENCE CONTROL REGISTER AND STILL ANOTHER RELATED REGISTER.