公开(公告)号：US20200083116A1

公开(公告)日：2020-03-12

申请号：US16567485

申请日：2019-09-11

Applicant: IMEC VZW

Inventor： Steven Demuynck ,  Geert Eneman ,  Vladimir Machkaoutsan

IPC: H01L21/8238 ,  H01L27/11 ,  H01L27/092 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66

Abstract: A method of forming gate contacts and/or contact lines on a plurality of fins. The method comprises providing a wafer comprising a semiconductor structure which comprises a plurality of fins. The method further comprises patterning at least one continuous trench over the fins, and filling at least one of the trenches with metal to obtain at least one continuous gate in contact with the fins and/or filling at least one of the trenches with metal to obtain at least one continuous contact line in contact with the fins. The method further comprises cutting the metal of the at least one gate and/or cutting the metal of the at least one contact line in between some of the fins.

公开(公告)号：US11088070B2

公开(公告)日：2021-08-10

申请号：US16936271

申请日：2020-07-22

Applicant: IMEC vzw

Inventor： Basoene Briggs ,  Vladimir Machkaoutsan ,  Zsolt Tokei

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A method of forming a multi-level interconnect structure in a semiconductor device is disclosed. In one aspect, the device includes a first interconnection level including a first dielectric layer and a first conductive structure; a second interconnection level including a second dielectric layer and a second conductive structure; and a third interconnection level including a third dielectric layer and a third conductive structure. The method includes forming a trench in the third dielectric layer; providing a first sacrificial material in the trench; and thereafter forming a via extending through the third interconnection level to the second conductive structure; providing a second sacrificial material in the via; forming a multi-level via extending through the third interconnection level to the first conductive structure; removing the first and second sacrificial materials; and depositing a conductive material at least partially filling: the trench; the via; and the multi-level via.

公开(公告)号：US20180076092A1

公开(公告)日：2018-03-15

申请号：US15704837

申请日：2017-09-14

Applicant: IMEC VZW

Inventor： Roel Gronheid ,  Vladimir Machkaoutsan

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/306 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/823431 ,  G03F7/0002 ,  H01L21/02118 ,  H01L21/02356 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/66795

Abstract: The present disclosure relates to methods and structures that involve the use of directed self-assembly to selectively remove at least one fin or fin section from a pattern of parallel fins in a semiconductor structure.

公开(公告)号：US20210028106A1

公开(公告)日：2021-01-28

申请号：US16936271

申请日：2020-07-22

Applicant: IMEC vzw

Inventor： Basoene Briggs ,  Vladimir Machkaoutsan ,  Zsolt Tokei

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: A method of forming a multi-level interconnect structure in a semiconductor device is disclosed. In one aspect, the device includes a first interconnection level including a first dielectric layer and a first conductive structure; a second interconnection level including a second dielectric layer and a second conductive structure; and a third interconnection level including a third dielectric layer and a third conductive structure. The method includes forming a trench in the third dielectric layer; providing a first sacrificial material in the trench; and thereafter forming a via extending through the third interconnection level to the second conductive structure; providing a second sacrificial material in the via; forming a multi-level via extending through the third interconnection level to the first conductive structure; removing the first and second sacrificial materials; and depositing a conductive material at least partially filling: the trench; the via; and the multi-level via.

公开(公告)号：US10186459B2

公开(公告)日：2019-01-22

申请号：US15704837

申请日：2017-09-14

Applicant: IMEC VZW

Inventor： Roel Gronheid ,  Vladimir Machkaoutsan

IPC: H01L21/82 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/306 ,  H01L21/762 ,  H01L21/02 ,  G03F7/00 ,  H01L29/66

Abstract: The present disclosure relates to methods and structures that involve the use of directed self-assembly to selectively remove at least one fin or fin section from a pattern of parallel fins in a semiconductor structure.