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    Gate, Contact, and Fin Cut Method
    1.
    发明申请
    Gate, Contact, and Fin Cut Method 审中-公开

    公开(公告)号：US20200083116A1

    公开(公告)日：2020-03-12

    申请号：US16567485

    申请日：2019-09-11

    Applicant: IMEC VZW

    Inventor： Steven Demuynck ,  Geert Eneman ,  Vladimir Machkaoutsan

    IPC: H01L21/8238 ,  H01L27/11 ,  H01L27/092 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66

    Abstract: A method of forming gate contacts and/or contact lines on a plurality of fins. The method comprises providing a wafer comprising a semiconductor structure which comprises a plurality of fins. The method further comprises patterning at least one continuous trench over the fins, and filling at least one of the trenches with metal to obtain at least one continuous gate in contact with the fins and/or filling at least one of the trenches with metal to obtain at least one continuous contact line in contact with the fins. The method further comprises cutting the metal of the at least one gate and/or cutting the metal of the at least one contact line in between some of the fins.

    STACKED SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME
    3.
    发明申请
    STACKED SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME 审中-公开

    公开(公告)号：US20200168606A1

    公开(公告)日：2020-05-28

    申请号：US16696935

    申请日：2019-11-26

    Applicant: IMEC vzw

    Inventor： Boon Teik Chan ,  Zheng Tao ,  Steven Demuynck

    IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/308 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L21/3065

    Abstract: The disclosed technology relates to a method of forming a stacked semiconductor device. One aspect includes fin structures formed by upper and lower channel layers which are separated by an intermediate layer. After preliminary fun cuts are formed in the fin structure, a sacrificial spacer is formed that covers end surfaces of an upper channel layer portion. Final fin cuts are formed in the fin structure where the lower channel layer is etched which defines a lower channel layer portion. Lower source/drain regions are formed on end surfaces of the lower channel layer portion. The sacrificial spacer shields the end surfaces of the upper channel layer portion allowing for selective deposition of material for the lower source/drain regions.

    Method for Forming Source/Drain Contacts
    4.
    发明申请
    Method for Forming Source/Drain Contacts 审中-公开

    公开(公告)号：US20190131411A1

    公开(公告)日：2019-05-02

    申请号：US16170674

    申请日：2018-10-25

    Applicant: IMEC VZW

    Inventor： Soon Aik Chew ,  Steven Demuynck

    IPC: H01L29/40 ,  H01L29/51 ,  H01L21/311 ,  H01L29/66 ,  H01L29/417 ,  H01L21/3105

    CPC classification number: H01L29/401 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/513 ,  H01L29/66795

    Abstract: Example embodiments relate to methods for forming source/drain contacts. One embodiment includes a method for forming a source contact and a drain contact in a semiconductor structure. The method includes providing a semiconductor structure that includes a semiconductor active area having channel, source, and drain regions, a gate structure on the channel region, a gate plug on the gate structure, spacers lining side walls of the gate structure and of the gate plug, an etch stop layer covering the source and gain regions, a sacrificial material on the etch stop layer over the source and drain regions, and a masking structure that masks the source and drain regions. The method also includes forming gaps, removing the masking structure, filling the gaps, exposing the sacrificial material, removing the sacrificial material, removing the etch stop layer, and forming the source contact and the drain contact by depositing a conductive material.

    Method for producing self-aligned gate and source/drain via connections for contacting a FET transistor
    5.
    发明授权
    Method for producing self-aligned gate and source/drain via connections for contacting a FET transistor 有权

    公开(公告)号：US11430876B2

    公开(公告)日：2022-08-30

    申请号：US17083125

    申请日：2020-10-28

    Applicant: IMEC vzw

    Inventor： Boon Teik Chan ,  Dunja Radisic ,  Steven Demuynck ,  Efrain Altamirano Sanchez ,  Soon Aik Chew

    IPC: H01L29/66 ,  H01L21/768

    Abstract: The disclosed technology is related to a method that includes the formation of contact vias for contacting gate electrodes and source (S) or drain (D) electrodes of nano-sized semiconductor transistors formed on a semiconductor wafer. The electrodes are mutually parallel and provided with dielectric gate and S/D plugs on top of the electrodes, and the mutually parallel electrode/plug assemblies are separated by dielectric spacers. The formation of the vias takes place by two separate self-aligned etch processes, the Vint-A etch for forming one or more vias towards one or more S/D electrodes and the Vint-G etch for forming one or more vias towards one or more gate electrodes. According to the disclosed technology, a conformal layer is deposited on the wafer after the first self-aligned etch process, wherein the conformal layer is resistant to the second self-aligned etch process. The conformal layer thereby protects the first contact via during the second self-aligned etch.

    Split Replacement Metal Gate Integration
    6.
    发明申请
    Split Replacement Metal Gate Integration 有权

    公开(公告)号：US20210118747A1

    公开(公告)日：2021-04-22

    申请号：US17074047

    申请日：2020-10-19

    Applicant: IMEC VZW

    Inventor： Eugenio Dentoni Litta ,  Boon Teik Chan ,  Steven Demuynck

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

    Abstract: A method for forming a semiconductor device, the method including: providing a substrate with at least one fin or nanowire; forming a dummy gate; providing spacers on the at least one fin or nanowire and the dummy gate; performing a first RMG module wherein high-k material is provided on at least one fin or nanowire, between the spacers; one or more annealing steps; providing a sacrificial plug between the spacers; epitaxially growing a source and drain in the at least one fin or nanowire; removing the sacrificial plug; performing a second RMG module wherein a WFM is deposited between at least part of the spacers such that the WFM is covering the high-k material of the at least one fin or nanowire.

    METHOD FOR PRODUCING SELF-ALIGNED GATE AND SOURCE/DRAIN VIA CONNECTIONS FOR CONTACTING A FET TRANSISTOR
    8.
    发明申请
    METHOD FOR PRODUCING SELF-ALIGNED GATE AND SOURCE/DRAIN VIA CONNECTIONS FOR CONTACTING A FET TRANSISTOR 有权

    公开(公告)号：US20210126108A1

    公开(公告)日：2021-04-29

    申请号：US17083125

    申请日：2020-10-28

    Applicant: IMEC vzw

    Inventor： Boon Teik Chan ,  Dunja Radisic ,  Steven Demuynck ,  Efrain Altamirano Sanchez ,  Soon Aik Chew

    IPC: H01L29/66 ,  H01L21/768

    Abstract: The disclosed technology is related to a method that includes the formation of contact vias for contacting gate electrodes and source (S) or drain (D) electrodes of nano-sized semiconductor transistors formed on a semiconductor wafer. The electrodes are mutually parallel and provided with dielectric gate and S/D plugs on top of the electrodes, and the mutually parallel electrode/plug assemblies are separated by dielectric spacers. The formation of the vias takes place by two separate self-aligned etch processes, the Vint-A etch for forming one or more vias towards one or more S/D electrodes and the Vint-G etch for forming one or more vias towards one or more gate electrodes. According to the disclosed technology, a conformal layer is deposited on the wafer after the first self-aligned etch process, wherein the conformal layer is resistant to the second self-aligned etch process. The conformal layer thereby protects the first contact via during the second self-aligned etch.

    Method for forming source/drain contacts
    9.
    发明授权
    Method for forming source/drain contacts 有权

    公开(公告)号：US10593765B2

    公开(公告)日：2020-03-17

    申请号：US16170674

    申请日：2018-10-25

    Applicant: IMEC VZW

    Inventor： Soon Aik Chew ,  Steven Demuynck

    IPC: H01L29/51 ,  H01L29/40 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/417 ,  H01L21/768

    Abstract: Example embodiments relate to methods for forming source/drain contacts. One embodiment includes a method for forming a source contact and a drain contact in a semiconductor structure. The method includes providing a semiconductor structure that includes a semiconductor active area having channel, source, and drain regions, a gate structure on the channel region, a gate plug on the gate structure, spacers lining side walls of the gate structure and of the gate plug, an etch stop layer covering the source and gain regions, a sacrificial material on the etch stop layer over the source and drain regions, and a masking structure that masks the source and drain regions. The method also includes forming gaps, removing the masking structure, filling the gaps, exposing the sacrificial material, removing the sacrificial material, removing the etch stop layer, and forming the source contact and the drain contact by depositing a conductive material.

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