APPARATUS FOR DETECTING LIQUID LEVEL

    公开(公告)号:US20170153139A1

    公开(公告)日:2017-06-01

    申请号:US14985183

    申请日:2015-12-30

    CPC classification number: G01F23/266 G01F23/268

    Abstract: An embodiment of the invention provides a liquid-level sensor to detect liquid-level information of a liquid to be tested in a container. The sensor includes an electrode, a sensing circuit, an amplifier and a controller. The electrode is disposed on the outer surface of the container, comprising a first electrode and a second electrode. The sensing circuit is coupled to a first electrode and a second electrode, and receives a clock signal to generate a first voltage signal and a second voltage signal. The amplifier receives the first voltage signal and the second voltage signal to output an output voltage. The controller acquires liquid-level information of the liquid to be tested according to the output voltage and a voltage-volume table.

    Apparatus for detecting liquid level

    公开(公告)号:US09983042B2

    公开(公告)日:2018-05-29

    申请号:US14985183

    申请日:2015-12-30

    CPC classification number: G01F23/266 G01F23/268

    Abstract: An embodiment of the invention provides a liquid-level sensor to detect liquid-level information of a liquid to be tested in a container. The sensor includes an electrode, a sensing circuit, an amplifier and a controller. The electrode is disposed on the outer surface of the container, comprising a first electrode and a second electrode. The sensing circuit is coupled to a first electrode and a second electrode, and receives a clock signal to generate a first voltage signal and a second voltage signal. The amplifier receives the first voltage signal and the second voltage signal to output an output voltage. The controller acquires liquid-level information of the liquid to be tested according to the output voltage and a voltage-volume table.

    Device and method for impedance analysis
    4.
    发明授权
    Device and method for impedance analysis 有权
    用于阻抗分析的装置和方法

    公开(公告)号:US09261566B2

    公开(公告)日:2016-02-16

    申请号:US14092759

    申请日:2013-11-27

    Abstract: An impedance analysis device adapted to an object under test (OUT) includes a signal generator, a signal analysis unit and a processing unit. The signal generator outputs a pulse signal to the OUT. The signal analysis unit acquires a response signal which the OUT responds to the pulse signal, and analyzes the response signal to obtain an analysis parameter. The processing unit coupled to the signal analysis unit receives the analysis parameter, so as to obtain an impedance variation characteristic of the OUT.

    Abstract translation: 适用于被测物(OUT)的阻抗分析装置包括信号发生器,信号分析单元和处理单元。 信号发生器向OUT输出脉冲信号。 信号分析单元获取OUT响应于脉冲信号的响应信号,并分析响应信号以获得分析参数。 耦合到信号分析单元的处理单元接收分析参数,以获得OUT的阻抗变化特性。

    Redundant processing node changing method and processor capable of changing redundant processing node

    公开(公告)号:US11314569B2

    公开(公告)日:2022-04-26

    申请号:US16729288

    申请日:2019-12-27

    Abstract: A processor capable of changing redundant processing node comprises a plurality of processing nodes and a plurality of comparators. The plurality of processing nodes comprises a first processing node, a second processing node, and a third processing node, wherein the first processing node performs a first computation, the second processing node selectively performs the first computation or a second computation, and the third processing node performs the second computation. The plurality of comparators comprises a first comparator and a second comparator, wherein the first comparator connects to the first and second processing nodes to compare whether the results of the first computation performed by the first and second processing nodes are identical, and the second comparator connects to the second and third processing nodes to compare whether results of the second computation performed by the second and third processing nodes are identical.

    Chip with embedded non-volatile memory and testing method therefor
    6.
    发明授权
    Chip with embedded non-volatile memory and testing method therefor 有权
    嵌入式非易失性存储器芯片及其测试方法

    公开(公告)号:US08867289B2

    公开(公告)日:2014-10-21

    申请号:US13727046

    申请日:2012-12-26

    CPC classification number: G11C29/00 G11C29/08 G11C29/16 G11C2029/0401

    Abstract: A testing method for a chip with an embedded non-volatile memory and the chip is provided. A remapping circuit and the non-volatile memory are connected to a processor. The non-volatile memory has a test area and an area under test. The test area stores a test program, and the area under test stores data under test. When the processor tests the chip, the processor outputs an original instruction address, and the remapping circuit remaps the original instruction address to generate a remapped instruction address. The processor reads the test program in the test area, and executes the test program to read the data under test in the area under test and to perform a test of toggling the logic circuit.

    Abstract translation: 提供了具有嵌入式非易失性存储器和芯片的芯片的测试方法。 重映射电路和非易失性存储器连接到处理器。 非易失性存储器具有测试区域和被测试区域。 测试区域存储测试程序,被测区域存储被测数据。 当处理器对芯片进行测试时,处理器输出原始指令地址,并且重新映射电路重新映射原始指令地址以生成重新映射的指令地址。 处理器读取测试区域中的测试程序,并执行测试程序以读取被测区域内的数据,并执行切换逻辑电路的测试。

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