公开(公告)号：US20140351616A1

公开(公告)日：2014-11-27

申请号：US14019546

申请日：2013-09-06

Applicant: Industrial Technology Research Institute ,  National Tsing Hua University ,  Chung Yuan Christian University

Inventor： Yow-Tyng Nieh ,  Shih-Chieh Chang ,  Chung-Han Chou ,  Shih-Hsu Huang

IPC: G06F1/32

CPC classification number: G06F1/10

Abstract: A voltage-controllable power-mode-aware (PMA) clock tree in an integrated circuit (IC) and a synthesis method and an operation method thereof are provided. The PMA clock tree includes at least two sub clock trees, at least two PMA buffers and a power mode control circuit. The at least two PMA buffers respectively delay a system clock and provide the delayed system clock to the sub clock trees as delayed clocks. The power mode control circuit respectively provides at least two first power information to at least two function modules to respectively determine the power modes of the function modules. The power mode control circuit respectively provides at least two second power information to the at least two PMA buffers to respectively determine the delay time of the PMA buffers.

Abstract translation: 提供集成电路（IC）中的电压可控功率模式感知（PMA）时钟树及其合成方法及其操作方法。 PMA时钟树包括至少两个子时钟树，至少两个PMA缓冲器和功率模式控制电路。 至少两个PMA缓冲器分别延迟系统时钟并将延迟的系统时钟提供给子时钟树作为延迟时钟。 功率模式控制电路分别向至少两个功能模块提供至少两个第一功率信息，以分别确定功能模块的功率模式。 功率模式控制电路分别向至少两个PMA缓冲器提供至少两个第二功率信息，以分别确定PMA缓冲器的延迟时间。

公开(公告)号：US09477258B2

公开(公告)日：2016-10-25

申请号：US14509055

申请日：2014-10-08

Applicant: Industrial Technology Research Institute ,  Chung Yuan Christian University ,  National Tsing Hua University

Inventor： Yow-Tyng Nieh ,  Shih-Hsu Huang ,  Shih-Chieh Chang ,  Chung-Han Chou

IPC: G06F1/00 ,  G06F1/32 ,  G06F17/50 ,  G06F1/10

CPC classification number: G06F1/10

Abstract: A clock tree in a circuit and an operation method thereof are provided. The clock tree includes at least two sub clock trees, at least two voltage-controllable power-mode-aware (PMA) buffers and a power-mode control circuit. The PMA buffers delay a system clock to serve as the delayed clock, and provide respectively the delayed clock to the sub clock trees. The power-mode control circuit provides at least two first power information to at least two function modules respectively, wherein a power mode of each of the function modules is determined according to the first power information respectively. The power-mode control circuit provides at least two second power information to the PMA buffers respectively, wherein a delay time of each of the PMA buffers is determined according to the second power information respectively.

Abstract translation: 提供电路中的时钟树及其操作方法。 时钟树包括至少两个子时钟树，至少两个电压可控功率模式感知（PMA）缓冲器和功率模式控制电路。 PMA缓冲器将系统时钟延迟用作延迟时钟，并分别向子时钟树提供延迟的时钟。 功率模式控制电路分别向至少两个功能模块提供至少两个第一功率信息，其中每个功能模块的功率模式分别根据第一功率信息来确定。 功率模式控制电路分别向PMA缓冲器提供至少两个第二功率信息，其中分别根据第二功率信息确定每个PMA缓冲器的延迟时间。

公开(公告)号：US20210192327A1

公开(公告)日：2021-06-24

申请号：US17131783

申请日：2020-12-23

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Shih-Chieh Chang ,  Shyh-Shyuan Sheu ,  Jian-Wei Su ,  Fu-Cheng Tsai

IPC: G06N3/063 ,  G06N3/04

Abstract: An apparatus and a method for neural network computation are provided. The apparatus for neural network computation includes a first neuron circuit and a second neuron circuit. The first neuron circuit is configured to execute a neural network computation of at least one computing layer with a fixed feature pattern in a neural network algorithm. The second neuron circuit is configured to execute the neural network computation of at least one computing layer with an unfixed feature pattern in the neural network algorithm. The performance of the first neuron circuit is greater than that of the second neuron circuit.

公开(公告)号：US12265904B2

公开(公告)日：2025-04-01

申请号：US17131783

申请日：2020-12-23

Applicant: Industrial Technology Research Institute

Inventor： Sih-Han Li ,  Shih-Chieh Chang ,  Shyh-Shyuan Sheu ,  Jian-Wei Su ,  Fu-Cheng Tsai

IPC: G06N3/063 ,  G06N3/045 ,  G06N3/0455

Abstract: An apparatus and a method for neural network computation are provided. The apparatus for neural network computation includes a first neuron circuit and a second neuron circuit. The first neuron circuit is configured to execute a neural network computation of at least one computing layer with a fixed feature pattern in a neural network algorithm. The second neuron circuit is configured to execute the neural network computation of at least one computing layer with an unfixed feature pattern in the neural network algorithm. The performance of the first neuron circuit is greater than that of the second neuron circuit.

公开(公告)号：US12260321B2

公开(公告)日：2025-03-25

申请号：US17385316

申请日：2021-07-26

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Fu-Cheng Tsai ,  Yi-Ching Kuo ,  Chih-Sheng Lin ,  Shyh-Shyuan Sheu ,  Tay-Jyi Lin ,  Shih-Chieh Chang

IPC: H03M1/12 ,  G06N3/04 ,  G06N3/063 ,  G11C27/02

Abstract: A data feature augmentation system and method for a low-precision neural network are provided. The data feature augmentation system includes a first time difference unit. The first time difference unit includes a first sample-and-hold circuit and a subtractor. The first sample-and-hold circuit is used for receiving an input signal and obtaining a first signal according to the input signal. The first signal is related to a first leakage rate of the first sample-and-hold circuit and the first signal is the signal generated by delaying the input signal by one time unit. The subtractor is used for performing subtraction on the input signal and the first signal to obtain a time difference signal. The input signal and the time difference signal are inputted to the low-precision neural network.

公开(公告)号：US20210004678A1

公开(公告)日：2021-01-07

申请号：US16846427

申请日：2020-04-13

Applicant: Industrial Technology Research Institute

Inventor： Shih-Chieh Chang ,  Sih-Han Li ,  Shyh-Shyuan Sheu ,  Jian-Wei Su ,  Heng-Yuan Lee

IPC: G06N3/08 ,  G11C11/54 ,  G06N3/04

Abstract: A neural circuit is provided. The neural circuit includes a neural array. The neural array includes a plurality of semiconductor components. Each of the semiconductor components stores a weighting value to generate a corresponding output current or a corresponding equivalent resistance. The neural array receives a plurality of input signals to control the semiconductor components in the neural array and respectively generates the output currents or changes the equivalent resistances. Since the semiconductor components are coupled to each other, output of the neural array may generate a summation current or a summation equivalent resistance related to the input signals and a weighting condition, so that a computing result exhibits high performance.

公开(公告)号：US20150026490A1

公开(公告)日：2015-01-22

申请号：US14509055

申请日：2014-10-08

Applicant: Industrial Technology Research Institute ,  Chung Yuan Christian University ,  National Tsing Hua University

Inventor： Yow-Tyng Nieh ,  Shih-Hsu Huang ,  Shih-Chieh Chang ,  Chung-Han Chou

IPC: G06F1/10 ,  G06F1/26

CPC classification number: G06F1/10

Abstract: A clock tree in a circuit and an operation method thereof are provided. The clock tree includes at least two sub clock trees, at least two voltage-controllable power-mode-aware (PMA) buffers and a power-mode control circuit. The PMA buffers delay a system clock to serve as the delayed clock, and provide respectively the delayed clock to the sub clock trees. The power-mode control circuit provides at least two first power information to at least two function modules respectively, wherein a power mode of each of the function modules is determined according to the first power information respectively. The power-mode control circuit provides at least two second power information to the PMA buffers respectively, wherein a delay time of each of the PMA buffers is determined according to the second power information respectively.

Abstract translation: 提供电路中的时钟树及其操作方法。 时钟树包括至少两个子时钟树，至少两个电压可控功率模式感知（PMA）缓冲器和功率模式控制电路。 PMA缓冲器将系统时钟延迟用作延迟时钟，并分别向子时钟树提供延迟的时钟。 功率模式控制电路分别向至少两个功能模块提供至少两个第一功率信息，其中每个功能模块的功率模式分别根据第一功率信息来确定。 功率模式控制电路分别向PMA缓冲器提供至少两个第二功率信息，其中分别根据第二功率信息确定每个PMA缓冲器的延迟时间。