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    MEMORY CELL
    1.
    发明公开
    MEMORY CELL 审中-公开

    公开(公告)号：US20240079051A1

    公开(公告)日：2024-03-07

    申请号：US17983331

    申请日：2022-11-08

    Applicant: Industrial Technology Research Institute

    Inventor： Chih-Sheng Lin ,  Tuo-Hung Hou ,  Fu-Cheng Tsai ,  Jian-Wei Su ,  Kuo-Hua Tseng

    IPC: G11C11/412 ,  G11C11/418

    CPC classification number: G11C11/412 ,  G11C11/418

    Abstract: Disclosed is a memory cell including a first transistor having a first terminal coupled to a bit line; a second transistor having a first terminal coupled to a bit line bar; a weight storage circuit coupled between a gate terminal of the first transistor and a gate terminal of the second transistor, storing a weight value, and determining to turn on the first transistor or the second transistor according to the weight value; and a driving circuit coupled to a second terminal of the first transistor, a second terminal of the second transistor, and at least one word line, receiving at least one threshold voltage and at least one input data from the word line, and determining whether to generate an operation current on a path of the turned-on first transistor or the turned-on second transistor according to the threshold voltage and the input data.

    Three-dimension symmetrical vertical transformer
    3.
    发明授权
    Three-dimension symmetrical vertical transformer 有权
    三维对称垂直变压器

    公开(公告)号：US09368271B2

    公开(公告)日：2016-06-14

    申请号：US14693866

    申请日：2015-04-22

    Applicant: Industrial Technology Research Institute

    Inventor： Sih-Han Li ,  Chih-Sheng Lin

    IPC: H01F5/00 ,  H01F27/28 ,  H01F27/29

    CPC classification number: H01F27/2804 ,  H01F5/00 ,  H01F27/2823 ,  H01F27/29 ,  H01F2027/2809

    Abstract: First and second paths of the primary-coil of the transformer are located at different sides of the symmetry-line. First terminals of the first and second paths are first and second ports of the primary-coil. Second terminals of the first and second paths are connected to each other. Two partial paths of the first path are connected to each other by TSV. Two partial paths of the second path are connected to each other by TSV. Third and fourth paths of the secondary-coil of the transformer are located on different sides of the symmetry-line. First terminals of the third and fourth paths are first and second ports of the secondary-coil. Second terminals of the third and fourth paths are connected to each other. Two partial paths of the third path are connected to each other by TSV. Two partial paths of the fourth path are connected to each other by TSV.

    Abstract translation: 变压器的初级线圈的第一和第二路径位于对称线的不同侧。 第一和第二路径的第一端子是初级线圈的第一和第二端口。 第一和第二路径的第二端子彼此连接。 第一路径的两个部分路径通过TSV相互连接。 第二路径的两个部分路径通过TSV相互连接。 变压器的次级线圈的第三和第四路径位于对称线的不同侧。 第三和第四路径的第一端子是次级线圈的第一和第二端口。 第三和第四路径的第二端子彼此连接。 第三路径的两个部分路径通过TSV相互连接。 第四路径的两个部分路径通过TSV相互连接。

    THREE-DIMENSION SYMMETRICAL VERTICAL TRANSFORMER
    4.
    发明申请
    THREE-DIMENSION SYMMETRICAL VERTICAL TRANSFORMER 有权
    三维对称垂直变压器

    公开(公告)号：US20160012958A1

    公开(公告)日：2016-01-14

    申请号：US14693866

    申请日：2015-04-22

    Applicant: Industrial Technology Research Institute

    Inventor： Sih-Han Li ,  Chih-Sheng Lin

    IPC: H01F27/28 ,  H01F27/29

    CPC classification number: H01F27/2804 ,  H01F5/00 ,  H01F27/2823 ,  H01F27/29 ,  H01F2027/2809

    Abstract: First and second paths of the primary-coil of the transformer are located at different sides of the symmetry-line. First terminals of the first and second paths are first and second ports of the primary-coil. Second terminals of the first and second paths are connected to each other. Two partial paths of the first path are connected to each other by TSV. Two partial paths of the second path are connected to each other by TSV. Third and fourth paths of the secondary-coil of the transformer are located on different sides of the symmetry-line. First terminals of the third and fourth paths are first and second ports of the secondary-coil. Second terminals of the third and fourth paths are connected to each other. Two partial paths of the third path are connected to each other by TSV. Two partial paths of the fourth path are connected to each other by TSV.

    Abstract translation: 变压器的初级线圈的第一和第二路径位于对称线的不同侧。 第一和第二路径的第一端子是初级线圈的第一和第二端口。 第一和第二路径的第二端子彼此连接。 第一路径的两个部分路径通过TSV相互连接。 第二路径的两个部分路径通过TSV相互连接。 变压器的次级线圈的第三和第四路径位于对称线的不同侧。 第三和第四路径的第一端子是次级线圈的第一和第二端口。 第三和第四路径的第二端子彼此连接。 第三路径的两个部分路径通过TSV相互连接。 第四路径的两个部分路径通过TSV相互连接。

    Readout circuit for sensor and readout method thereof
    7.
    发明授权
    Readout circuit for sensor and readout method thereof 有权

    公开(公告)号：US10914618B2

    公开(公告)日：2021-02-09

    申请号：US15851609

    申请日：2017-12-21

    Applicant: Industrial Technology Research Institute

    Inventor： Sih-Han Li ,  Chih-Sheng Lin ,  Ya-Wen Yang ,  Kuan-Wei Chen ,  Shyh-Shyuan Sheu

    IPC: G01D18/00 ,  G01D3/02

    Abstract: A readout circuit for a sensor and a readout method thereof are provided. The readout circuit includes a reference circuit, a compensated circuit, and a signal processing circuit. The reference circuit provides a direct current (DC) signal. The compensated circuit is coupled to the reference circuit. The compensated circuit obtains an analog sensing signal of the sensor, obtains the DC signal from the reference circuit, and provides a compensated signal according to the analog sensing signal and the DC signal. The signal processing circuit is coupled to the compensated circuit. The signal processing circuit processes the compensated signal to convert the compensated signal into a digital sensing signal. The compensated circuit subtracts the DC signal from the analog sensing signal to provide the compensated signal.

    Memory circuit with sense amplifier calibration mechanism
    8.
    发明授权
    Memory circuit with sense amplifier calibration mechanism 有权

    公开(公告)号：US12142342B2

    公开(公告)日：2024-11-12

    申请号：US18074528

    申请日：2022-12-05

    Applicant: Industrial Technology Research Institute

    Inventor： Chih-Sheng Lin ,  Fu-Cheng Tsai ,  Tuo-Hung Hou ,  Jian-Wei Su ,  Yu-Hui Lin ,  Chih-Ming Lai

    IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

    Abstract: According to an exemplary embodiments, the disclosure is directed to a memory circuit which includes not limited to a first half sense amplifier circuit connected to a first plurality of memory cells through a first bit line and configured to receive a unit of analog electrical signal from each of the first plurality of memory cells and to generate a first half sense amplifier output signal corresponding to the first bit line based on a first gain of the half sense amplifier and an accumulation of the units of analog signals, a locking code register circuit configured to receive a locking data and to generate a digital locking sequence, and a source selector circuit configured to receive the digital locking sequence and to generate a first adjustment signal to adjust the first half sense amplifier output signal corresponding to the first bit line by adjusting the first gain.

    Computing in memory cell
    9.
    发明授权
    Computing in memory cell 有权

    公开(公告)号：US11599600B2

    公开(公告)日：2023-03-07

    申请号：US17013646

    申请日：2020-09-06

    Applicant: Industrial Technology Research Institute

    Inventor： Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou ,  Sih-Han Li ,  Fu-Cheng Tsai ,  Yu-Hui Lin

    IPC: G11C11/412 ,  G06F17/16

    Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.

    Memory device and data weight state determining method for in-memory computation
    10.
    发明授权
    Memory device and data weight state determining method for in-memory computation 有权

    公开(公告)号：US11423983B2

    公开(公告)日：2022-08-23

    申请号：US17322509

    申请日：2021-05-17

    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

    Inventor： Chih-Sheng Lin ,  Sih-Han Li ,  Yu-Hui Lin ,  Jian-Wei Su

    IPC: G11C11/00 ,  G11C13/00 ,  G11C7/06

    Abstract: A memory device for in-memory computation includes data channels, a memory cell array, a maximum accumulated weight generating array, a minimum accumulated weight generating array, a reference generator and a comparator. The data channels are selectively enabled according to data input. The memory cell array generates an accumulated data weight value according to the quantity of enabled data channels, a first resistance and a second resistance. The maximum accumulated weight generating array generates a maximum accumulated weight value according to the quantity of enabled data channels and the first resistance. The minimum accumulated weight generating array generates a minimum accumulated weight value according to the quantity of enabled data channels and the second resistance. The reference generator generates reference value(s) according to the maximum and minimum accumulated weight values. The comparator compares the accumulated data weight value with the reference value(s) to generate a data weight state.

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