公开(公告)号：US20230403865A1

公开(公告)日：2023-12-14

申请号：US18455449

申请日：2023-08-24

申请人： INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY ,  INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY ERICA CAMPUS

发明人： Jongill HONG ,  Saeroonter OH

IPC分类号： H10B61/00 ,  H03K19/17728 ,  H03K19/18 ,  H01F10/32 ,  H10N59/00 ,  H10N50/80 ,  H10N50/85

CPC分类号： H10B61/00 ,  H03K19/17728 ,  H03K19/18 ,  H01F10/3272 ,  H01F10/3286 ,  H01F10/3254 ,  H01F10/329 ,  H10N59/00 ,  H10N50/80 ,  H10N50/85

摘要： Disclosed are a spin logic device based on spin-charge conversion and a spin logic array using the same. A reconfigurable spin logic array according to an exemplary embodiment of the present invention may include: an input terminal receiving at least three current signals; a plurality of wires transmitting the current signal in connection with the input terminal and including a horizontal wire and a vertical wire which cross each other; a first gate array in which at least one first majority gate connected to the input terminal through the wires and implemented based on the spin logic device is arranged; and a second gate array in which at least one second majority gate connected to the first gate array through the wires and implemented based on the spin logic device is arranged.

公开(公告)号：US20240186422A1

公开(公告)日：2024-06-06

申请号：US18242005

申请日：2023-09-05

申请人： Samsung Display Co., Ltd. ,  Industry-University Cooperation Foundation Hanyang University ERICA CAMPUS

发明人： JOON SEOK PARK ,  Saeroonter OH ,  Su Hyun KIM ,  Taeho LEE ,  MYOUNGHWA KIM ,  JUN HYUNG LIM

IPC分类号： H01L29/786 ,  H10K59/121

CPC分类号： H01L29/7869 ,  H10K59/1213

摘要： Provided is a transistor including a first electrode, an active layer disposed under the first electrode and having a hole pattern with at least one hole in the source region, a drain region, and an active region overlapping the first electrode, and a second electrode disposed under the active layer. At least one of the first electrode and the second electrode overlaps the hole pattern. This way, the area of the transistor may be reduced, thereby achieving a display panel having a narrow bezel and reducing parasitic capacitance.

公开(公告)号：US20240049510A1

公开(公告)日：2024-02-08

申请号：US18312637

申请日：2023-05-05

申请人： Samsung Display Co., LTD. ,  Industry-University Cooperation Foundation Hanyang University ERICA Campus

发明人： Joon Seok PARK ,  Saeroonter OH ,  Su Hyun KIM ,  Taeho LEE ,  Hye Lim CHOI ,  Jun Hyung LIM

IPC分类号： H10K59/121 ,  H10K59/124

CPC分类号： H10K59/1216 ,  H10K59/124

摘要： According to an embodiment, a display device includes: a first capacitor electrode disposed on a substrate to include a first conductive layer and a second conductive layer disposed on the first conductive layer; a buffer layer disposed on the first capacitor electrode; a second capacitor electrode disposed on the buffer layer; a driving transistor disposed on the substrate; and a storage capacitor disposed on the substrate and electrically connected to the driving transistor, wherein the first capacitor electrode includes a concave portion and a convex portion depending on a pattern of the second conductive layer disposed on the first conductive layer, the buffer layer and the second capacitor electrode each include protrusions and depressions corresponding to the concave portion and the convex portion of the first capacitor electrode, and the first capacitor electrode and the second capacitor electrode form two electrodes of the storage capacitor.

公开(公告)号：US20210408195A1

公开(公告)日：2021-12-30

申请号：US17313046

申请日：2021-05-06

申请人： Samsung Display Co., Ltd. ,  Industry-University Cooperation Foundation Hanyang University ERICA Campus

发明人： Sang Woo SOHN ,  Saeroonter OH ,  Joon Seok PARK ,  Young Joon CHOI ,  Su Hyun KIM ,  Jun Hyung LIM

IPC分类号： H01L27/32 ,  H01L51/56 ,  G09G3/3225

摘要： A display device comprises a substrate; a driving transistor including a first active layer and a switching transistor including a second active layer, the first active layer and the second active layer being disposed on the substrate; a first gate insulating layer disposed on the first active layer of the driving transistor and the second active layer of the switching transistor; first and second gate electrodes disposed on the first gate insulating layer to overlap the first active layer of the driving transistor and the second active layer of the switching transistor, respectively; a first interlayer insulating layer disposed on the first gate electrode and the second gate electrode; and a second interlayer insulating layer disposed on the first interlayer insulating layer to overlap the first active layer without overlapping the second active layer in a plan view.

公开(公告)号：US20240179964A1

公开(公告)日：2024-05-30

申请号：US18434812

申请日：2024-02-07

申请人： Samsung Display Co., Ltd. ,  Industry-University Cooperation Foundation Hanyang University ERICA Campus

发明人： Sang Woo SOHN ,  Saeroonter OH ,  Joon Seok PARK ,  Young Joon CHOI ,  Su Hyun KIM ,  Jun Hyung LIM

IPC分类号： H10K59/126 ,  G09G3/3225 ,  H10K59/131 ,  H10K71/00

CPC分类号： H10K59/126 ,  G09G3/3225 ,  H10K59/131 ,  H10K71/00

摘要： A display device comprises a substrate; a driving transistor including a first active layer and a switching transistor including a second active layer, the first active layer and the second active layer being disposed on the substrate; a first gate insulating layer disposed on the first active layer of the driving transistor and the second active layer of the switching transistor; first and second gate electrodes disposed on the first gate insulating layer to overlap the first active layer of the driving transistor and the second active layer of the switching transistor, respectively; a first interlayer insulating layer disposed on the first gate electrode and the second gate electrode; and a second interlayer insulating layer disposed on the first interlayer insulating layer to overlap the first active layer without overlapping the second active layer in a plan view.

公开(公告)号：US20220207340A1

公开(公告)日：2022-06-30

申请号：US17610027

申请日：2020-05-21

申请人： INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY ERICA CAMPUS ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

发明人： Saeroonter OH ,  Sangbum KIM

IPC分类号： G06N3/063

摘要： A synapse-mimetic device includes: a capacitor; a first transistor which connects a first power supply to a first end of the capacitor in response to a first control signal; a second transistor which connects a second power supply to a second end of the capacitor in response to a second control signal; a third transistor which connects the first power supply to the second end of the capacitor in response to a third control signal; a fourth transistor which connects the second power supply to the first end of the capacitor in response to a fourth control signal; and a fifth transistor which provides, to an output line, a current determined by the voltage of the first end of the capacitor, the voltage of the input line, and the voltage of the output line.

公开(公告)号：US20220085071A1

公开(公告)日：2022-03-17

申请号：US17232211

申请日：2021-04-16

申请人： Samsung Display Co., LTD. ,  Industry-University Cooperation Foundation Hanyang University ERICA Campus

发明人： Hye Lim CHOI ,  Saeroonter OH ,  Kihwan KIM ,  Joon Seok PARK ,  Ji Hwan LEE ,  Jun Hyung LIM

IPC分类号： H01L27/12

摘要： An embodiment of the present invention provides a display device including a substrate and a transistor on the substrate. The transistor includes: a lower layer having conductivity and including a body portion and a plurality of protrusions; an oxide semiconductor layer including a channel region, a first conductive region disposed at a first side of the channel region, and a second conductive region disposed at a second side of the channel region, where the second side is opposite the first side; a gate electrode overlapping the channel region in a plan view; a first electrode electrically connected to the first conductive region; and a second electrode electrically connected to the second conductive region. The plurality of protrusions protrudes from the body portion, and the body portion overlaps the channel region in the plan view.