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公开(公告)号:US20240357941A1
公开(公告)日:2024-10-24
申请号:US18763018
申请日:2024-07-03
Inventor: William J. Gallagher
CPC classification number: H10N50/01 , H01F41/34 , H01L21/0332 , H10B61/00 , H10N50/80 , H01F10/3254 , H01F10/329
Abstract: Some examples relate to an integrated circuit. The integrated circuit comprises a semiconductor substrate, a bottom electrode over the substrate, a circular magnetic tunneling junction (MTJ) disposed over an upper surface of bottom electrode, and a circular top electrode disposed over an upper surface of the magnetic tunneling junction. The circular top electrode is concentric to the circular magnetic tunneling junction, and a diameter of the circular magnetic tunneling junction is smaller than 60 nm or smaller than 30 nm.
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公开(公告)号:US12108684B2
公开(公告)日:2024-10-01
申请号:US17315345
申请日:2021-05-09
Applicant: HeFeChip Corporation Limited
Inventor: Qinli Ma , Wei-Chuan Chen , Youngsuk Choi , Shu-Jen Han
CPC classification number: H10N50/80 , G11C11/161 , H01F10/3254 , H01F10/329 , H10B61/22 , H10N50/85 , H01F10/3286
Abstract: A magnetic tunneling junction (MTJ) element includes a reference layer, a tunnel barrier layer on the reference layer, a free layer on the tunnel barrier layer, and a composite capping layer on the free layer. The composite capping layer comprises a diffusion-stop layer on the free layer, a light-element sink layer on the diffusion-stop layer, and an amorphous layer on the light-element sink layer.
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公开(公告)号:US20240315147A1
公开(公告)日:2024-09-19
申请号:US18677654
申请日:2024-05-29
Inventor: Ji-Feng YING , Jhong-Sheng WANG , Tsann LIN
CPC classification number: H10N50/80 , G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675 , H01F10/3254 , H01F10/329 , H10B61/22 , H10N50/01 , H10N50/85 , H10N52/80
Abstract: A magnetic memory includes a first spin-orbital-transfer-spin-torque-transfer (SOT-STT) hybrid magnetic device disposed over a substrate, a second SOT-STT hybrid magnetic device disposed over the substrate, and a SOT conductive layer connected to the first and second SOT-STT hybrid magnetic devices. Each of the first and second SOT-STT hybrid magnetic devices includes a first magnetic layer, as a magnetic free layer, a spacer layer disposed under the first magnetic layer, and a second magnetic layer, as a magnetic reference layer, disposed under the spacer layer. The SOT conductive layer is disposed over the first magnetic layer of each of the first and second SOT-STT hybrid magnetic devices.
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公开(公告)号:US20240284803A1
公开(公告)日:2024-08-22
申请号:US17772765
申请日:2020-10-30
Applicant: TOHOKU UNIVERSITY
Inventor: Tetsuo Endoh , Yoshiaki Saito , Shoji Ikeda , Hideo Sato
CPC classification number: H10N50/85 , H01F10/3254 , H01F10/329 , H10B61/00 , H10N50/10
Abstract: Provided are a tunnel junction stacked film having a high thermal stability, and a magnetic memory element and a magnetic memory using the tunnel junction stacked film. A tunnel junction stacked film 1 includes a recording layer 14 including a first ferromagnetic layer 24 containing boron, a tunnel junction layer 13 adjacent to the recording layer 14, and a reference layer 12 adjacent to the tunnel junction layer 13, wherein the first ferromagnetic layer 24 and the reference layer 12 are magnetized in a perpendicular direction with respect to a film surface, and the recording layer 14 includes a hafnium layer 25 adjacent to the first ferromagnetic layer 24.
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公开(公告)号:US12058940B2
公开(公告)日:2024-08-06
申请号:US17873315
申请日:2022-07-26
Inventor: William J. Gallagher
CPC classification number: H10N50/01 , H01F41/34 , H01L21/0332 , H10B61/00 , H10N50/80 , H01F10/3254 , H01F10/329
Abstract: Some examples relate to an integrated circuit. The integrated circuit comprises a semiconductor substrate, a bottom electrode over the substrate, a circular magnetic tunneling junction (MTJ) disposed over an upper surface of bottom electrode, and a circular top electrode disposed over an upper surface of the magnetic tunneling junction. The circular top electrode is concentric to the circular magnetic tunneling junction, and a diameter of the circular magnetic tunneling junction is smaller than 60 nm or smaller than 30 nm.
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公开(公告)号:US12035636B2
公开(公告)日:2024-07-09
申请号:US18140472
申请日:2023-04-27
Inventor: Ji-Feng Ying , Jhong-Sheng Wang , Tsann Lin
CPC classification number: H10N50/80 , G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675 , H01F10/3254 , H01F10/329 , H10B61/22 , H10N50/01 , H10N50/85 , H10N52/80
Abstract: A magnetic memory includes a first spin-orbital-transfer-spin-torque-transfer (SOT-STT) hybrid magnetic device disposed over a substrate, a second SOT-STT hybrid magnetic device disposed over the substrate, and a SOT conductive layer connected to the first and second SOT-STT hybrid magnetic devices. Each of the first and second SOT-STT hybrid magnetic devices includes a first magnetic layer, as a magnetic free layer, a spacer layer disposed under the first magnetic layer, and a second magnetic layer, as a magnetic reference layer, disposed under the spacer layer. The SOT conductive layer is disposed over the first magnetic layer of each of the first and second SOT-STT hybrid magnetic devices.
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公开(公告)号:US12029137B2
公开(公告)日:2024-07-02
申请号:US17521017
申请日:2021-11-08
Applicant: EVERSPIN TECHNOLOGIES, INC.
Inventor: Sumio Ikegawa
CPC classification number: H10N50/80 , G11C11/161 , H01F10/3254 , H01F10/3272 , H01F10/3286 , H01F10/329 , H01F41/32 , H10N50/01 , H10N50/10 , H10N50/85
Abstract: A magnetoresistive device comprises a fixed magnetic region positioned on or over a first electrically conductive region, an intermediate layer positioned on or over the fixed magnetic region, a free magnetic region positioned on or over the intermediate layer, and a metal insertion substance positioned in contact with the free magnetic region, wherein the metal insertion substance includes one or more transition metal elements.
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公开(公告)号:US20240112840A1
公开(公告)日:2024-04-04
申请号:US17956786
申请日:2022-09-29
Applicant: Western Digital Technologies, Inc.
Inventor: Susumu OKAMURA , Quang LE , Brian R. YORK , Cherngye HWANG , Randy G. SIMMONS , Kuok San HO , Hisashi TAKANO
CPC classification number: H01F10/329 , C22C19/07 , G11B5/39 , H01L27/222 , H01L43/04 , H01L43/06 , H01L43/10 , G11B2005/0024
Abstract: Embodiments of the present disclosure relate to a cobalt-boron (CoB) layer for magnetic recording devices, memory devices, and storage devices. In one or more embodiments, the CoB layer is part of a spin-orbit torque (SOT) device. In one or more embodiments, the SOT device is part of an SOT based sensor, an SOT based writer, a memory device (such as a magnetoresistive random-access memory (MRAM) device), and/or a storage device (such as a hard disk drive (HDD) or a tape drive). In one embodiment, an SOT device includes a seed layer, and a cap layer spaced from the seed layer. The SOT device includes a spin-orbit torque (SOT) layer, and a nano layer (NL) between the seed layer and the cap layer. The SOT device includes a cobalt-boron (CoB) layer between the seed layer and the cap layer, and the CoB layer is ferromagnetic.
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公开(公告)号:US11894172B2
公开(公告)日:2024-02-06
申请号:US17290118
申请日:2018-11-06
Applicant: TDK CORPORATION
Inventor: Tetsuhito Shinohara
CPC classification number: H01F10/3272 , H01F10/329 , H01F10/3286 , H01L27/105 , H01L29/82 , H10B99/00 , H10N50/10 , H10N50/80 , H10N50/85 , H01F10/3254 , H10B61/00
Abstract: A domain wall moving type magnetic recording element includes: a domain wall moving layer in which first layers containing a rare earth metal and second layers containing a transition metal are alternately stacked in a first direction; and a first electrode and a second electrode which face the domain wall moving layer and are arranged to be away from each other. The domain wall moving layer has SOT suppression parts which are positioned in one of interfaces between the first layers and the second layers and contain a non-magnetic metal. The SOT suppression parts are locally distributed at the interface.
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公开(公告)号:US11881263B2
公开(公告)日:2024-01-23
申请号:US17221670
申请日:2021-04-02
Applicant: Arm Limited
Inventor: Akhilesh Ramlaut Jaiswal , Mudit Bhargava
IPC: G11C14/00 , G11C11/16 , G11C11/418 , G11C11/419 , H01F10/32 , G11C13/00 , H10N50/80 , H10N50/85
CPC classification number: G11C14/0081 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C11/1675 , G11C11/418 , G11C11/419 , G11C11/161 , G11C13/004 , G11C13/0007 , G11C13/0026 , G11C13/0028 , G11C13/0069 , G11C14/009 , G11C2213/31 , G11C2213/32 , H01F10/329 , H01F10/3254 , H10N50/80 , H10N50/85
Abstract: Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate transfer of stored values between the volatile and non-volatile memory bitcells.
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